| Patent Number |
Title Of Patent |
Date Issued |
| 7511644 |
Variable resistance logic |
March 31, 2009 |
| A system comprising a control logic that generates a code having n digits, a translation logic coupled to the control logic that translates the code to a new code having greater than n digits, and a variable resistance logic coupled to the translation logic and comprising greater than n |
| 7511534 |
Circuits, devices, systems, and methods of operation for a linear output driver |
March 31, 2009 |
| Embodiments are described for an output driver circuit capable of maintaining a substantially constant output impedance across a wide range of output voltages. The driver circuit includes a pull-up circuit and a pull-down circuit, each having two or more current paths that either sou |
| 7511531 |
Temperature-compensated output buffer |
March 31, 2009 |
| A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up |
| 7511520 |
Universal wafer carrier for wafer level die burn-in |
March 31, 2009 |
| A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electric |
| 7511364 |
Floating lead finger on a lead frame, lead frame strip, and lead frame assembly including same |
March 31, 2009 |
| A semiconductor device assembly includes a semiconductor device and a lead frame having lead fingers for connection to the semiconductor device. The lead frame may include floating no connect (NC) lead fingers with inner portions of the floating NC lead fingers electrically isolated from |
| 7511363 |
Copper interconnect |
March 31, 2009 |
| An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on |
| 7511356 |
Voltage-controlled semiconductor inductor and method |
March 31, 2009 |
| A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a |
| 7511354 |
Well for CMOS imager and method of formation |
March 31, 2009 |
| A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second |
| 7511341 |
SOI device having increased reliability and reduced free floating body effects |
March 31, 2009 |
| The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium passivation anneal by electrically pre-stressing the fabricated device prior to a deuterium anneal. The method of the present invent |
| 7511326 |
ALD of amorphous lanthanide doped TiO.sub.x films |
March 31, 2009 |
| The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiO.sub.x) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The |
| 7511262 |
Optical device and assembly for use with imaging dies, and wafer-label imager assembly |
March 31, 2009 |
| Microelectronic imagers with integrated optical devices and methods for manufacturing imagers. The imagers, for example, typically have an imaging unit including a first substrate and an image sensor on and/or in the first substrate. An embodiment of an optical device includes a stan |
| 7510983 |
Iridium/zirconium oxide structure |
March 31, 2009 |
| Embodiments of an electronic apparatus and embodiments for methods of forming the electronic apparatus include a conductive layer having an iridium-based layer, where the conductive layer is disposed on a dielectric layer containing zirconium oxide. In various embodiments, each of th |
| 7510966 |
Electrically conductive line, method of forming an electrically conductive line, and method of r |
March 31, 2009 |
| The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an |
| 7510961 |
Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect str |
March 31, 2009 |
| A method for manufacturing an interconnect structure situated on a semiconductor wafer having a substrate assembly thereon. The interconnect structure is formed in a recess such as a trench, a hole, a via, or a combination of a trench and a hole or via within a dielectric material si |
| 7510954 |
Memory array with surrounding gate access transistors and capacitors with global and staggered l |
March 31, 2009 |
| A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memo |
| 7510897 |
Photodiode with self-aligned implants for high quantum efficiency and method of formation |
March 31, 2009 |
| A pinned photodiode with a pinned surface layer formed by a self-aligned angled implant is disclosed. The angle of the implant may be tailored to provide an adequate offset between the pinned surface layer and an electrically active area of a transfer gate of the pixel sensor cell. The |
| 7509543 |
Circuit and method for error test, recordation, and repair |
March 24, 2009 |
| In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. |
| 7509474 |
Robust index storage for non-volatile memory |
March 24, 2009 |
| A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address |
| 7509005 |
Resistive heater for thermo optic device |
March 24, 2009 |
| Resistive heaters formed in two mask counts on a surface of a grating of a thermo optic device thereby eliminating one mask count from prior art manufacturing methods. The resistive heater is comprised of a heater region and a conductive path region formed together in a first mask count |
| 7508722 |
Memory device having strobe terminals with multiple functions |
March 24, 2009 |
| A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The |
| 7508708 |
NAND string with a redundant memory cell |
March 24, 2009 |
| The invention provides methods and apparatus. A NAND memory block has a source select line for selectively coupling one or more strings of series-coupled non-volatile memory cells to a source line, a drain select line for selectively coupling one or more strings of series-coupled non |
| 7508648 |
Atomic layer deposition of Dy doped HfO.sub.2 films as gate dielectrics |
March 24, 2009 |
| The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO.sub.2) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the d |
| 7508075 |
Self-aligned poly-metal structures |
March 24, 2009 |
| A semiconductor structure is provided comprising a self-aligned poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly-metal stack. A semiconduc |
| 7508074 |
Etch stop layer in poly-metal structures |
March 24, 2009 |
| In accordance with one embodiment of the present invention, a semiconductor structure is provided comprising a poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along |
| 7508025 |
Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulato |
March 24, 2009 |
| Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second |
| 7508024 |
Three dimensional flash cell |
March 24, 2009 |
| A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures. |
| 7508016 |
CMOS imager having on-chip ROM |
March 24, 2009 |
| A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other manufacturing production data. Testing results and repair solutions are written to the ROM after production testing. A simple circ |
| 7507672 |
Plasma etching system and method |
March 24, 2009 |
| A system and a process for plasma etching a semiconductor device. The technique comprises periodically applying a heightened voltage bias during the plasma etching process so as to reduce accumulated charge on the surface of the semiconductor device during plasma etching of the devic |
| 7506226 |
System and method for more efficiently using error correction codes to facilitate memory device |
March 17, 2009 |
| A memory device includes an ECC and test circuit. In a normal mode, the circuit performs ECC conventional functions. In a test mode, the least significant bit of received data is used to generate test data. If the received bit is "0," the test data bits are all "0," and if the received |
| 7506146 |
Fast and compact circuit for bus inversion |
March 17, 2009 |
| A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the |
| 7506126 |
Detection circuit for mixed asynchronous and synchronous memory operation |
March 17, 2009 |
| A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal i |
| 7505357 |
Column/row redundancy architecture using latches programmed from a look up table |
March 17, 2009 |
| A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address |
| 7505341 |
Low voltage sense amplifier and sensing method |
March 17, 2009 |
| Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is |
| 7505330 |
Phase-change random access memory employing read before write for resistance stabilization |
March 17, 2009 |
| An improved architecture and method for operating a PCRAM integrated circuit is disclosed which seeks to minimize degradation in the resistance of the phase change material in the cells. When an attempt is made during a write command to write a data state to a bit which already has t |
| 7505323 |
Programming memory devices |
March 17, 2009 |
| A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the |
| 7505317 |
Method, apparatus, and system for providing initial state random access memory |
March 17, 2009 |
| A memory device comprising memory cells having volatile and non-volatile memory portions. The volatile memory portion of each cell includes circuitry for performing RAM functions while the non-volatile memory portion comprises circuitry defining pre-coded data. The memory device comp |
| 7505309 |
Static RAM memory cell with DNR chalcogenide devices and method of forming |
March 17, 2009 |
| An SRAM memory device having improved stability including two series connected devices, at least one of the devices being a chalcogenide device exhibiting differential negative resistance characteristics. One of the two devices serves as the load of the other. A switch is provided to |
| 7504767 |
Electrode structures, display devices containing the same |
March 17, 2009 |
| An electrode structure for a display device comprising a gate electrode proximate to an emitter and a focusing electrode separated from the gate electrode by an insulating layer containing a ridge are provided. When the focusing electrode is an aperture-type electrode, the ridge protrude |
| 7504730 |
Memory elements |
March 17, 2009 |
| Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as |
| 7504687 |
Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulato |
March 17, 2009 |
| Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second |
| 7504685 |
Oxide epitaxial isolation |
March 17, 2009 |
| Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxi |
| 7504674 |
Electronic apparatus having a core conductive structure within an insulating layer |
March 17, 2009 |
| Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive layer to a H.sub.2 |
| 7504310 |
Semiconductors bonded on glass substrates |
March 17, 2009 |
| A method includes providing a glass substrate and bonding a semiconductor layer to the glass substrate. The semiconductor layer is formed to a thickness such that it does not yield due to temperature-induced strain at device processing temperatures. |
| 7504298 |
Method for forming memory cell and device |
March 17, 2009 |
| A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells |
| 7504285 |
Carrierless chip package for integrated circuit devices, and methods of making same |
March 17, 2009 |
| Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductivel |
| 7504284 |
Microelectronic device packages, stacked microelectronic device packages, and methods for manufa |
March 17, 2009 |
| A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made |
| 7503046 |
Method of obtaining interleave interval for two data values |
March 10, 2009 |
| A method of determining an interleave pattern for n lots of A and y lots of B, when n plus y equals a power of two such that the expression 2.sup.z-n may be used to represent the value of y, includes generating a key including the reverse bit order of a serially indexed count from 0 to |
| 7503002 |
Text based markup language resource interface |
March 10, 2009 |
| A software control method and apparatus for displaying a text based markup language interface. The interface can interact with a computer to provide reference documents, install system drivers and perform various system utilities. The interface can reference optical drivers, hard disk dr |
| 7502659 |
Sorting a group of integrated circuit devices for those devices requiring special testing |
March 10, 2009 |
| A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing includes storing fabrication deviation data, probe data, and test data in association with |
| 7502058 |
Imager with tuned color filter |
March 10, 2009 |
| An optimized color filter array is formed in, above or below a one or more damascene layers. The color filter array includes filter regions which are configured to optimize the combined optical properties of the layers of the device to maximize the intensity of the particular wavelength |
