| Patent Number |
Title Of Patent |
Date Issued |
| 7518422 |
Switched capacitor for a tunable delay circuit |
April 14, 2009 |
| A method and apparatus is provided for providing a fine delay by switching on a capacitor delay. A coarse delay and/or a fine delay are implemented upon a reference signal based upon a phase shift between the reference signal and a feedback signal. A fine delay is implemented upon the |
| 7518302 |
Method of fabricating field emission arrays employing a hard mask to define column lines and ano |
April 14, 2009 |
| Each pixel of a field emission device includes a resistor with at least one emitter tip thereover and at least one substantially vertically oriented conductive element positioned adjacent the resistor. In a field emission array, a conductive element may contact each resistor of a line |
| 7518246 |
Atomic layer deposition of CeO.sub.2/Al.sub.2O.sub.3 films as gate dielectrics |
April 14, 2009 |
| The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a |
| 7518237 |
Microfeature systems including adhered microfeature workpieces and support members |
April 14, 2009 |
| Methods and systems for adhering microfeature workpieces to support members are disclosed. A method in accordance with one embodiment of the invention includes disposing a first adhesive on a surface of a microfeature workpiece, and disposing a second adhesive on a surface of a suppo |
| 7518227 |
Multiple die stack apparatus employing T-shaped interposer elements |
April 14, 2009 |
| Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof are disclosed. |
| 7518223 |
Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer |
April 14, 2009 |
| A semiconductor device that includes at least one nonconfluent spacer layer on at least one surface thereof. The at least one nonconfluent spacer layer at least partially spaces the surface of the semiconductor device apart from another semiconductor device assembled in stacked arran |
| 7518212 |
Graded Ge.sub.xSe.sub.100-x concentration in PCRAM |
April 14, 2009 |
| The present invention provides a design for a PCRAM element which incorporates multiple metal-containing germanium-selenide glass layers of diverse stoichiometries. The present invention also provides a method of fabricating the disclosed PCRAM structure. |
| 7518184 |
DRAM access transistor |
April 14, 2009 |
| Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sac |
| 7518182 |
DRAM layout with vertical FETs and method of formation |
April 14, 2009 |
| DRAM cell arrays having a cell area of about 4F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally |
| 7518174 |
Memory cell and method for forming the same |
April 14, 2009 |
| A semiconductor memory cell structure having 4F.sup.2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active r |
| 7517798 |
Methods for forming through-wafer interconnects and structures resulting therefrom |
April 14, 2009 |
| The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing |
| 7517797 |
Carrier for wafer-scale package, wafer-scale package including the carrier, and methods |
April 14, 2009 |
| A carrier for use in a chip-scale package includes a semiconductor substrate with a plurality of apertures formed therethrough. The apertures of the carrier are aligned with bond pads of a semiconductor device. Conductive material is introduced into each of the apertures of the carri |
| 7517786 |
Methods of forming wire bonds for semiconductor constructions |
April 14, 2009 |
| The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a fir |
| 7517783 |
Molybdenum-doped indium oxide structures and methods |
April 14, 2009 |
| Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain molybdenum are deposited onto a substrate and subsequently processed to form molybdenum-doped indium oxide. The resulting transpa |
| 7517758 |
Method of forming a vertical transistor |
April 14, 2009 |
| The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first po |
| 7517754 |
Methods of forming semiconductor constructions |
April 14, 2009 |
| The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also |
| 7517753 |
Methods of forming pluralities of capacitors |
April 14, 2009 |
| The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes anodically etching individual capacitor electrode channels within a material over individual capacitor storage node locations on a substr |
| 7517749 |
Method for forming an array with polysilicon local interconnects |
April 14, 2009 |
| Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing |
| 7517744 |
Capacitorless DRAM on bulk silicon |
April 14, 2009 |
| A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon subst |
| 7517743 |
Fully-depleted (FD) (SOI) MOSFET access transistor and method of fabrication |
April 14, 2009 |
| A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed. |
| 7517704 |
MRAM layer having domain wall traps |
April 14, 2009 |
| A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory |
| 7517558 |
Methods for positioning carbon nanotubes |
April 14, 2009 |
| The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment, the device includes a substrate and a plurality of funnels in the substrate, wherein each of the funnels comprises an inlet o |
| 7516363 |
System and method for on-board diagnostics of memory modules |
April 7, 2009 |
| A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device inte |
| 7516300 |
Active memory processing array topography and method |
April 7, 2009 |
| An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying instructions to the processing elements. The processing elements are logically arranged in a plurality of logical rows and logical |
| 7516281 |
On-die termination snooping for 2T applications in a memory system implementing non-self-termina |
April 7, 2009 |
| A method and apparatus for controlling the on-die termination of a memory system. The method comprises snooping a command bus in response to a first plurality of command signals clocked at 1T and enabling the on-die termination in response to a second plurality of command signals clocked |
| 7516271 |
Obtaining search results based on match signals and search width |
April 7, 2009 |
| Content addressable memory (CAM) in which search results such as an address code and an array match signal can be obtained for multiple search widths. The CAM includes a CAM array that can provide match signals and suppress signals for memory locations. Match combining circuitry comb |
| 7515501 |
Memory architecture having local column select lines |
April 7, 2009 |
| A memory architecture for an array of memory cells having a plurality of sections of memory and a plurality of regions disposed between the plurality of sections of memory. Each section of memory having a plurality of memory cells arranged in rows and columns of memory and a pluralit |
| 7515485 |
External clock tracking pipelined latch scheme |
April 7, 2009 |
| A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data bits, a command decoder coupled to the first latch output; a command latch including a first command latch input, a second c |
| 7515481 |
Memory block erasing in a flash memory device |
April 7, 2009 |
| The erase and verify method performs an erase operation and an erase verify read operation. If the erase verify read operation fails because unerased memory cells have been found, a normal memory read operation is performed in order to determine which memory cells are still programmed. |
| 7515188 |
Method and system for reducing mismatch between reference and intensity paths in analog to digit |
April 7, 2009 |
| A circuit for reducing a mismatch between a reference path to which a reference voltage is applied and an intensity path to which an intensity voltage is applied from an active pixel sensor comprises a first and a second pair of switches and a processing circuit. The first pair of sw |
| 7514991 |
High accuracy current mode duty cycle and phase placement sampling circuit |
April 7, 2009 |
| A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock signals is provided. The duty cycle and phase placement sampling circuit includes dual differential input stages and re-time |
| 7514982 |
Methods, devices and systems for sensing the state of fuse devices |
April 7, 2009 |
| A fuse sensing circuit includes a sense controller and a fuse state sensor. The sense controller includes a reference fuse and a reference sensor coupled to the reference fuse. The reference sensor generates a sample clock with a certain threshold transition characteristic in respons |
| 7514979 |
De-emphasis system and method for coupling digital signals through capacitively loaded lines |
April 7, 2009 |
| A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digit |
| 7514954 |
Method and apparatus for output driver calibration |
April 7, 2009 |
| An output driver calibration circuit determines calibration values for configuring adjustable impedance output drivers. Output drivers are calibrated by generating a first variable count in response to comparing a reference voltage to a first voltage at a calibration terminal when an |
| 7514945 |
Systems configured for utilizing semiconductor components |
April 7, 2009 |
| The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets. The sockets can be configured so that compression of the sockets opens a clamping mechanism. A chip can be placed within a socket |
| 7514776 |
Semiconductor/printed circuit board assembly, and computer system |
April 7, 2009 |
| A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the seco |
| 7514366 |
Methods for forming shallow trench isolation |
April 7, 2009 |
| A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls |
| 7514324 |
Selective epitaxy in vertical integrated circuit |
April 7, 2009 |
| Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of the component body. |
| 7514291 |
Methods relating to singulating semiconductor wafers and wafer scale assemblies |
April 7, 2009 |
| Methods relating to singulation of dice from semiconductor wafers. Trenches or channels are formed in the bottom surface of a semiconductor wafer, corresponding in location to wafer streets. The trenches may be formed by etching or through an initial laser cut. The wafer is then sing |
| 7513182 |
Integrated circuit package separators |
April 7, 2009 |
| Integrated circuit package separator for separating integrated circuit packages from a board. A base having a plurality of pins extending upwardly therefrom is provided. A support is provided over the base. The support has an upper surface and a plurality of holes extending therethro |
| 7512910 |
Integrated circuit design using charge pump modeling |
March 31, 2009 |
| Circuit models for the simulation of charge pumps facilitate design of integrated circuits containing charge pumps. Such models facilitate accurate simulation of actual charge pump behavior without the need to rigorously simulate the multiple capacitive stages of an actual charge pum |
| 7512909 |
Read strobe feedback in a memory system |
March 31, 2009 |
| A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed back to |
| 7512763 |
Transparent SDRAM in an embedded environment |
March 31, 2009 |
| A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part because it can function without precharge signals, row address latch signals, and column |
| 7512507 |
Die based trimming |
March 31, 2009 |
| Methods and structures are described to provide trims for die on a wafer. The trims are set on a die-by-die basis instead of a wafer basis. Accordingly, the individual die are more finely tuned and more die operate at the target specifications so that yield is increased. In an embodi |
| 7512170 |
Method of forming mirrors by surface transformation of empty spaces in solid state materials |
March 31, 2009 |
| A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped empty space patterns are formed by drilling holes in the substrate and annealing the substrate to form the spaced-apart pla |
| 7512029 |
Method and apparatus for managing behavior of memory devices |
March 31, 2009 |
| A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power |
| 7512025 |
Open digit line array architecture for a memory array |
March 31, 2009 |
| A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines |
| 7512019 |
High speed digital signal input buffer and method using pulsed positive feedback |
March 31, 2009 |
| An input buffer generates an output signal corresponding to a digital input signal. The input buffer is coupled to a feedback circuit. The feedback circuit initially couples a positive feedback signal to the buffer circuit responsive to each transition of the input signal. The positi |
| 7511994 |
MEM suspended gate non-volatile memory |
March 31, 2009 |
| A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing floating gate to floating gate coupling and leakage current, and increasing data retention. |
| 7511984 |
Phase change memory |
March 31, 2009 |
| A PCRAM cell has a high resistivity bottom electrode cap to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements. |
