| Patent Number |
Title Of Patent |
Date Issued |
| 7531453 |
Microelectronic devices and methods for forming interconnects in microelectronic devices |
May 12, 2009 |
| Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate |
| 7531443 |
Method and system for fabricating semiconductor components with through interconnects and back s |
May 12, 2009 |
| A method for fabricating semiconductor components includes the step of providing a semiconductor substrate having a circuit side, a back side, a plurality of integrated circuits on the circuit side, and a plurality of substrate contacts on the circuit side in electrical communication wit |
| 7531421 |
Semiconductor capacitor structure and method to form same |
May 12, 2009 |
| A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material. The semiconductor capacitor |
| 7531395 |
Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect tra |
May 12, 2009 |
| Methods of forming layers comprising epitaxial silicon, and methods of forming field effect transistors are disclosed. A method of forming a layer comprising epitaxial silicon includes etching an opening into a silicate glass-comprising material received over a monocrystalline materi |
| 7531379 |
Method of forming CMOS imager with capacitor structures |
May 12, 2009 |
| A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an act |
| 7531373 |
Methods of forming a conductive interconnect in a pixel of an imager and in other integrated cir |
May 12, 2009 |
| A method of forming conductive interconnects includes forming a node of a circuit component on a substrate. A conductive metal line is formed at a first metal routing level that is elevationally outward of the circuit component. Insulative material is deposited above the first metal rout |
| 7530877 |
Semiconductor processor systems, a system configured to provide a semiconductor workpiece proces |
May 12, 2009 |
| Semiconductor processor systems, systems configured to provide a semiconductor workpiece process fluid, semiconductor workpiece processing methods, methods of preparing semiconductor workpiece process fluid, and methods of delivering semiconductor workpiece process fluid to a semicon |
| 7529969 |
Memory device internal parameter reliability |
May 5, 2009 |
| Embodiments herein may store redundant copies of an operational parameter associated with an internal operation of a memory device. The redundant copies and associated parity bits may be stored in sets of writeable, non-volatile storage cells. A working area of the memory device may |
| 7529951 |
Memory subsystem voltage control and method that reprograms a preferred operating voltage |
May 5, 2009 |
| A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a nonvolatile memory configured to store a preferred memory device voltage configuration corresponding to a preferred operati |
| 7529896 |
Memory modules having a memory hub containing a posted write buffer, a memory device interface a |
May 5, 2009 |
| A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are also posted in the buffe |
| 7529882 |
Dynamic volume management for flash memories |
May 5, 2009 |
| A method for managing a range of memory in a flash memory space in which a plurality of data objects are stored. A volume defined for the range of memory has a first end and second end, with a respective list of data objects associated with each end. The volume can be resized, moved, and |
| 7529460 |
Zinc oxide optical waveguides |
May 5, 2009 |
| The present disclosure includes methods, devices, and systems having zinc oxide waveguides for optical signal interconnections. One optical signal interconnect system includes an oxide layer on a semiconductor substrate. A ZnO waveguide can be provided in the oxide layer and connected to |
| 7529318 |
Circuit and method for reducing noise interference in digital differential input receivers |
May 5, 2009 |
| A circuit and method reduces noise signals coupled to a reference voltage used by a digital differential input receiver having an input that is coupled to an input/output terminal. The circuit and method selectively isolates the reference voltage from the input/output terminal to which |
| 7529273 |
Method and system for synchronizing communications links in a hub-based memory system |
May 5, 2009 |
| A method is disclosed for synchronizing communications links in a memory hub system. The system includes a system controller and a plurality of memory hubs coupled in series, with pairs of downstream and upstream links being coupled between adjacent modules and the controller. The me |
| 7529129 |
Single level cell programming in a multiple level cell non-volatile memory device |
May 5, 2009 |
| A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire data into either the least significant or most significant bit of the cell. A second programming operation the programs rei |
| 7528877 |
Method and system for reducing mismatch between reference and intensity paths in analog to digit |
May 5, 2009 |
| A circuit for reducing a mismatch between a reference path to which a reference voltage is applied and an intensity path to which an intensity voltage is applied from an active pixel sensor comprises a first and a second pair of switches and a processing circuit. The first pair of sw |
| 7528638 |
Clock signal distribution with reduced parasitic loading effects |
May 5, 2009 |
| Clock signal distribution systems with reduced parasitic loading effects are provided. A reference clock is frequency-divided to produce a lower frequency clock signal. A delay-locked loop (DLL) circuit locks to the lower frequency clock signal, and outputs a corresponding lower frequenc |
| 7528624 |
Output buffer and method having a supply voltage insensitive slew rate |
May 5, 2009 |
| An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transis |
| 7528536 |
Protective layer for corrosion prevention during lithography and etch |
May 5, 2009 |
| Forming a protective layer such as chromium, chrome alloys, nickel or cobalt as a cap over an aluminum film protects an underlying ITO layer from corrosion during the fabrication of flat panel displays such as field emission devices and the like. The presence of the protective layer |
| 7528491 |
Semiconductor components and assemblies including vias of varying lateral dimensions |
May 5, 2009 |
| Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a second opening, and a third opening are formed in a substrate such that the first opening, the second opening, and the third openin |
| 7528477 |
Castellation wafer level packaging of integrated circuit chips |
May 5, 2009 |
| Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are |
| 7528440 |
Vertical gain cell |
May 5, 2009 |
| A vertical cell is realized. The cell includes a first vertical metal oxide semiconductor (MOS) transistor having a body between a drain region and a source region and a second vertical MOS transistor including at least a portion of the body of the first vertical MOS transistor. |
| 7528439 |
Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory |
May 5, 2009 |
| A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrica |
| 7528435 |
Semiconductor constructions |
May 5, 2009 |
| The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions being nearer the dielectric material than the other. The portion of the metal nitride nearest the dielectric material is formed |
| 7528430 |
Electronic systems |
May 5, 2009 |
| The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the se |
| 7528424 |
Integrated circuitry |
May 5, 2009 |
| This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline mater |
| 7528401 |
Agglomeration elimination for metal sputter deposition of chalcogenides |
May 5, 2009 |
| A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the meth |
| 7528064 |
Interconnect structures with bond-pads and methods of forming bump sites on bond-pads |
May 5, 2009 |
| Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-p |
| 7528043 |
Scalable gate and storage dielectric |
May 5, 2009 |
| Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric |
| 7528037 |
Flash memory having a high-permittivity tunnel dielectric |
May 5, 2009 |
| A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed above the substrate. |
| 7528007 |
Methods for assembling semiconductor devices and interposers |
May 5, 2009 |
| A method for assembling one or more semiconductor devices with an interposer includes positioning the one or more semiconductor devices within a receptacle that extends through the interposer, on a retention element that extends over at least a portion of the receptacle. Material may |
| 7527693 |
Apparatus for improved delivery of metastable species |
May 5, 2009 |
| The invention includes a deposition system having a reservoir for containment of a metastable specie connected to a deposition chamber. The system includes a metastable specie generating catalyst within the reservoir. The invention also includes an atomic layer deposition apparatus h |
| 7527545 |
Methods and tools for controlling the removal of material from microfeature workpieces |
May 5, 2009 |
| Methods and apparatus for controlling the removal of material from microfeature workpieces in abrasive removal processes. An embodiment of such a method comprises irradiating a periodic structure of the workpiece and obtaining an intensity distribution of radiation returning from the |
| 7526795 |
Data security for digital data storage |
April 28, 2009 |
| A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may be network resident. The data encryption may utilize a key which is derived at least in part from an identification code stored |
| 7526713 |
Low power cost-effective ECC memory system and method |
April 28, 2009 |
| A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words written to the DRAM, and the |
| 7526709 |
Error detection and correction in a CAM |
April 28, 2009 |
| An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching functions) the error detection and correction circuit tests all of the CAM locations that i |
| 7526704 |
Testing system and method allowing adjustment of signal transmit timing |
April 28, 2009 |
| A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing circuit includes a ring buffer into which the respective memory device signal is latched responsive to a first clock signal. The |
| 7526095 |
Audio volume control for computer systems |
April 28, 2009 |
| A computer system includes an audio chip to generate audio signals at a target volume level to be emitted as audio output by speakers. Also included in the computer system may be a volume control routine to limit the overall volume level of the system. A maximum volume level may be set |
| 7525842 |
Increased NAND flash memory read throughput |
April 28, 2009 |
| A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of f |
| 7525841 |
Programming method for NAND flash |
April 28, 2009 |
| A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells utilizing a drain-side self boost, modified drain-side self boost or local self boost process that increases the pass voltage (V |
| 7525458 |
Method and apparatus for converting parallel data to serial data in high speed applications |
April 28, 2009 |
| A method and apparatus to convert parallel data to serial data is provided. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline configured to receive parallel data, and binary sort logic comprising a plurality of switches arranged to receive |
| 7525379 |
Low voltage CMOS differential amplifier |
April 28, 2009 |
| There is provided a device including a PMOS differential amplifier and an NMOS differential amplifier. The NMOS differential amplifier is coupled to the PMOS differential amplifier. The device is configured to operate as an inverter when a supply voltage is below a predetermined threshol |
| 7525354 |
Local coarse delay units |
April 28, 2009 |
| Methods, circuits, devices, and systems are provided, including embodiments with local coarse delay units. One embodiment includes generating a first delayed signal, a second delayed signal, and a third delayed signal by delaying a clock reference signal with various time delays of a |
| 7525352 |
Current differential buffer |
April 28, 2009 |
| A memory device having a differential buffer is disclosed. In some embodiments, the memory device includes a differential buffer having a differential pair that is configured to receive input signals and generate output signals. In one embodiment, the differential buffer of the memor |
| 7525332 |
On-chip substrate regulator test mode |
April 28, 2009 |
| An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating voltage level of the substrate. This is accomplished with a chain of MOSFETs that are configured to operate as a chain of |
| 7525164 |
Strained Si/SiGe/SOI islands and processes of making same |
April 28, 2009 |
| A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A thermal oxidation com |
| 7525149 |
Combined volatile and non-volatile memory device with graded composition insulator stack |
April 28, 2009 |
| A memory device is fabricated with a graded composition tunnel insulator layer. This layer is formed over a substrate with a drain and a source region. The tunnel insulator is comprised of a graded SiC--GeC--SiC composition. A charge blocking layer is formed over the tunnel insulator. |
| 7525141 |
Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit |
April 28, 2009 |
| A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally u |
| 7525134 |
CMOS imager pixel designs |
April 28, 2009 |
| A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an act |
| 7524756 |
Process of forming a semiconductor assembly having a contact structure and contact liner |
April 28, 2009 |
| A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a conductive spacer liner |
