| Patent Number |
Title Of Patent |
Date Issued |
| 7541270 |
Methods for forming openings in doped silicon dioxide |
June 2, 2009 |
| Methods of forming openings in doped silicon dioxide layers and of forming self aligned contact holes are provided. The openings are generally etched in a plasma processing chamber. An etchant gas mixture comprising at least one fluorocarbon gas, at least one hydrogen containing gas, and |
| 7541242 |
NROM memory cell, memory array, related devices and methods |
June 2, 2009 |
| An array of memory cells configured to store at least one bit per one F.sup.2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory f |
| 7541081 |
Phase change memory for archival data storage |
June 2, 2009 |
| A structure for storing digital data is provided, with a high reflectance layer comprising a noble metal formed over an underlying material layer, and a plurality of low reflectance portions comprising a mixture of a noble metal and an underlying material. The plurality of low reflectanc |
| 7540018 |
Data security for digital data storage |
May 26, 2009 |
| A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may be network resident. The data encryption may utilize a key which is derived at least in part from an identification code stored |
| 7539921 |
Parity bit system for a CAM |
May 26, 2009 |
| A CAM includes a parity bit system for error detection. In one embodiment, in each CAM cell, the data portion has its own data parity bit while the status portion has an independent status parity bit. The status parity bit is recalculated and updated whenever a status bit in the entry is |
| 7539896 |
Repairable block redundancy scheme |
May 26, 2009 |
| A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when certain input block addresses are received. The new addresses are loaded into a programmable fuse latch each time an address |
| 7539062 |
Interleaved memory program and verify method, device and system |
May 26, 2009 |
| An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a |
| 7539052 |
Non-volatile multilevel memory cell programming |
May 26, 2009 |
| Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold |
| 7539048 |
Method and apparatus processing variable resistance memory cell write operation |
May 26, 2009 |
| A circuit and method for writing to a variable resistance memory cell. The circuit includes a variable resistance memory cell, a switchable current blocking device and a charge storing element. As the switchable current blocking device blocks current flow through the variable resistance |
| 7538880 |
Turbidity monitoring methods, apparatuses, and sensors |
May 26, 2009 |
| Semiconductor processors, sensors, semiconductor processing systems, semiconductor workpiece processing methods, and turbidity monitoring methods are provided. According to one aspect, a semiconductor processor includes a process chamber configured to receive a semiconductor workpiec |
| 7538858 |
Photolithographic systems and methods for producing sub-diffraction-limited features |
May 26, 2009 |
| Systems and methods for near-field photolithography utilize surface plasmon resonances to enable imaging of pattern features that exceed the diffraction limit. An example near-field photolithography system includes a plasmon superlens template including a plurality of opaque features to |
| 7538801 |
Region-based auto gain control and auto exposure control method and apparatus |
May 26, 2009 |
| An apparatus and method for performing automatic exposure and gain control while minimizing oscillations as well as providing a good response time, for example, a lag time or a settling time of about one frame. The automatic exposure and gain controls are performed not only on the image |
| 7538702 |
Quantizing circuits with variable parameters |
May 26, 2009 |
| Systems, methods, and devices, such as a device including a floating-gate transistor, a quantizing circuit coupled to the floating-gate transistor, and a controller configured to vary a voltage of a gate of the floating-gate transistor when reading data from the floating-gate transis |
| 7538590 |
Methods and apparatus for dividing a clock signal |
May 26, 2009 |
| There is provided a true single phase logic clock divider that is configured to divide a clock signal by increments of two, three, four, or six. Because the true single phase logic clock divider is based on true single phase logic instead of static logic, the true single phase logic |
| 7538572 |
Off-chip driver apparatus, systems, and methods |
May 26, 2009 |
| Apparatus, methods, and systems include an off-chip driver having an output drive coupled in parallel with the off-chip driver to provide initial drive emphasis for a period of time. The output drive may include a first transistor and a second transistor coupled to an output of the o |
| 7538413 |
Semiconductor components having through interconnects |
May 26, 2009 |
| A semiconductor component includes a semiconductor substrate having a substrate contact on a circuit side thereof in electrical communication with an integrated circuit, and a through interconnect in physical and electrical contact with the substrate contact configured to provide a s |
| 7538392 |
Pseudo SOI substrate and associated semiconductor devices |
May 26, 2009 |
| The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a |
| 7538389 |
Capacitorless DRAM on bulk silicon |
May 26, 2009 |
| A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon subst |
| 7538372 |
Twin p-well CMOS imager |
May 26, 2009 |
| A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in the doped area. The invention also provides a CMOS imager where a photodetector sensor array is formed in a first p-well and read |
| 7538036 |
Methods of forming openings, and methods of forming container capacitors |
May 26, 2009 |
| A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned |
| 7538028 |
Barrier layer, IC via, and IC line forming methods |
May 26, 2009 |
| A barrier layer forming method includes providing a porous dielectric layer over a substrate, the dielectric layer having a surface with exposed pores, and treating the dielectric layer with a plasma formed from a methane-containing gas. The treating seals the exposed pores. The meth |
| 7538001 |
Transistor gate forming methods and integrated circuits |
May 26, 2009 |
| A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as |
| 7537994 |
Methods of forming semiconductor devices, assemblies and constructions |
May 26, 2009 |
| Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material |
| 7537966 |
Method for fabricating board on chip (BOC) semiconductor package with circuit side polymer layer |
May 26, 2009 |
| A method for fabricating a BOC package includes the steps of providing a semiconductor die having planarized bumps encapsulated in a polymer layer, and providing a substrate having a plurality of conductors and an opening. The method also includes the steps of attaching the die to the |
| 7537804 |
ALD methods in which two or more different precursors are utilized with one or more reactants to |
May 26, 2009 |
| In some embodiments, the invention may include utilization of at least one iteration of an ALD pulse sequence that has the pulse subsets M.sub.2-M.sub.1-R- and M.sub.1-(R-M.sub.2-).sub.x: where x is at least 2; where M.sub.1 is a first metal-containing precursor comprising a first me |
| 7537511 |
Embedded fiber acoustic sensor for CMP process endpoint |
May 26, 2009 |
| Devices, systems and methods for monitoring characteristics of semiconductor substrates and workpieces during planarization and for endpointing planarization processes are provided. The invention utilizes a fiber optic contact sensor incorporated into a planarizing pad or pad-subpad |
| 7536618 |
Wide frequency range signal generator and method, and integrated circuit test system using same |
May 19, 2009 |
| A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a toggling flip-flop. The frequency of the output clock signal is adjusted by selecting the flip-flop to which the input clock signal is |
| 7535759 |
Memory system with user configurable density/performance option |
May 19, 2009 |
| The memory system has one or more memory dies coupled to a processor or other system controller. Each die has a separate memory array organized into multiple memory blocks. The different memory blocks of each die can be assigned a different memory density by the end user, depending on th |
| 7535695 |
DRAM cells and electronic systems |
May 19, 2009 |
| The invention includes capacitor constructions which have a layer of aluminum oxide between a high-k dielectric material and a layer containing titanium and nitrogen. The layer containing titanium and nitrogen can be, for example, titanium nitride and/or boron-doped titanium nitride. |
| 7535282 |
Dynamic well bias controlled by Vt detector |
May 19, 2009 |
| The p- well back bias for NCH transistors in a DRAM sense amplifier circuit is dynamically adjusted. Preferably, during sensing, the p- well back bias for the NCH transistors of the sense amp is increased to in effect lower the threshold voltages for the NCH transistors so that they |
| 7535281 |
Reduced time constant charge pump and method for charging a capacitive load |
May 19, 2009 |
| A charge pump and method converts an input voltage to a boosted voltage having a magnitude or polarity that is different from that of the input voltage. The input voltage is adjusted so that it has a relatively large magnitude until the boosted voltage approaches a target voltage. Th |
| 7535250 |
Output impedance calibration circuit with multiple output driver models |
May 19, 2009 |
| A method and circuitry for calibration of the output impedance of output driver circuits in an integrated circuit is disclosed. The output drivers within an area on the integrated circuit are defined as a group, and an output model indicative of the operation of the output drivers and us |
| 7535112 |
Semiconductor constructions comprising multi-level patterns of radiation-imageable material |
May 19, 2009 |
| The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a fir |
| 7535103 |
Structures and methods to enhance copper metallization |
May 19, 2009 |
| Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. T |
| 7535054 |
Trench corner effect bidirectional flash memory cell |
May 19, 2009 |
| A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being lined with a trapping material. The trench is filled with an oxide dielectric material and a control gate is formed over the |
| 7535048 |
NROM memory cell, memory array, related devices and methods |
May 19, 2009 |
| An array of memory cells configured to store at least one bit per one F.sup.2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory f |
| 7535047 |
Semiconductor device containing an ultra thin dielectric film or dielectric layer |
May 19, 2009 |
| An ultra thin dielectric film or dielectric layer on a semiconductor device is disclosed. In one embodiment, an oxide layer is formed over a substrate. A silicon-containing material is deposited over the oxide layer. The deposited material and oxide layer are processed in a plasma to |
| 7534982 |
Reduced imager crosstalk and pixel noise using extended buried contacts |
May 19, 2009 |
| Methods and structures to reduce the occurrence of crosstalk and pixel noise in solid state imager arrays. In an exemplary embodiment, a section of a layer patterned to form polysilicon buried-contacts in the pixel structure is also patterned to be disposed over the active, photosensor |
| 7534694 |
Methods of forming a plurality of capacitors |
May 19, 2009 |
| The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a substrate. Individual of the capacitor electrode openings are bounded on a first pair of opposing sides by a first capacitor electr |
| 7534681 |
Memory device fabrication |
May 19, 2009 |
| The invention provides methods of fabricating memory devices. One embodiment forms a bulk insulation layer overlying a plurality of source/drain regions formed in a substrate, removes a cap layer formed on each of a plurality of gate stacks formed on the substrate to expose an upper |
| 7534660 |
Methods for assembly and packaging of flip chip configured dice with interposer |
May 19, 2009 |
| A method for assembly and packaging of one or more flip chip-configured semiconductor dice with an interposer substrate to form a flip chip-type semiconductor device assembly. The flip chip-type semiconductor device assembly includes a conductively bumped semiconductor die and an int |
| 7533665 |
Dicing saw blade positioning apparatus and methods independent of blade thickness via constraine |
May 19, 2009 |
| An apparatus for positioning dicing saw blades at a fixed axial distance from one another independent of the thicknesses of the saw blades, where the saw blade thickness varies within a range. Flanges, spacers, and retention elements may be employed to achieve desired spacing of dicing |
| 7533350 |
Multiple operating system quick boot utility |
May 12, 2009 |
| A computerized user interface for assisting a computer user selects a default operating system for a computer. The computerized interface operates during a current computing session and provides a list of operating systems available. A user can make a selection using standard activat |
| 7533213 |
Memory hub and method for memory system performance monitoring |
May 12, 2009 |
| A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics--for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, read rate, number of |
| 7532532 |
System and method for hidden-refresh rate modification |
May 12, 2009 |
| A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second |
| 7532524 |
Bitline exclusion in verification operation |
May 12, 2009 |
| Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a |
| 7532517 |
Non-volatile one time programmable memory |
May 12, 2009 |
| A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further programming or erasing is inhibited. In another embodiment, the memory block can be programmed and erased until a predetermined page |
| 7532053 |
Phase interpolation apparatus, systems, and methods |
May 12, 2009 |
| A phase interpolator circuit may comprise a multiplexer circuit (MUX) to receive a plurality of clock signals at MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital |
| 7531906 |
Flip chip packaging using recessed interposer terminals |
May 12, 2009 |
| A method and apparatus for packaging a semiconductor die with an interposer substrate. A semiconductor device assembly includes a conductively bumped semiconductor die and an interposer substrate having multiple recesses formed therein. The semiconductor die is mounted to the interpo |
| 7531869 |
Lanthanum aluminum oxynitride dielectric films |
May 12, 2009 |
| Electronic apparatus and methods of forming the electronic apparatus include a lanthanum aluminum oxynitride film on a substrate for use in a variety of electronic systems. The lanthanum aluminum oxynitride film may be structured as one or more monolayers. |
