| Patent Number |
Title Of Patent |
Date Issued |
| 7547978 |
Underfill and encapsulation of semiconductor assemblies with materials having differing properti |
June 16, 2009 |
| Polymerized materials for forming the underfill and encapsulation structures for semiconductor package are disclosed. A filler constituent, such as boron nitride, silicates, elemental metals, or alloys, may be added to a liquid photopolymer resin to tailor the physical properties the |
| 7547954 |
Electronic systems using optical waveguide interconnects formed through a semiconductor wafer |
June 16, 2009 |
| An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high |
| 7547949 |
Semiconductor structures and memory device constructions |
June 16, 2009 |
| The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extendin |
| 7547945 |
Transistor devices, transistor structures and semiconductor constructions |
June 16, 2009 |
| The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly rela |
| 7547935 |
Semiconductor devices including buried digit lines that are laterally offset from corresponding |
June 16, 2009 |
| A method of electrically linking contacts of a semiconductor device to their corresponding digit lines. The method includes disposing a quantity of mask material into a trench through which the contact is exposed. The mask also abuts a connect region of a conductive element of a corr |
| 7547905 |
Programmable conductor memory cell structure and method therefor |
June 16, 2009 |
| In programmable conductor memory cells, metal ions precipitate out of a glass electrolyte element in response to an applied electric field in one direction only, causing a conductive pathway to grow from cathode to anode. The amount of conductive pathway growth, and therefore the pro |
| 7547877 |
Microelectronic imagers with integrated optical devices and methods for manufacturing such micro |
June 16, 2009 |
| Microelectronic imagers with integrated optical devices and methods for manufacturing imagers. The imagers, for example, typically have an imaging unit including a first substrate and an image sensor on and/or in the first substrate. An embodiment of an optical device includes a stan |
| 7547850 |
Semiconductor device assemblies with compliant spring contact structures |
June 16, 2009 |
| Photolithography patterned spring contacts are disclosed. The spring contacts may be fabricated using thin film processing techniques. A substrate, such as a silicon wafer or a carrier substrate is provided. At least one layer of a metal or alloy film may be deposited on the substrat |
| 7547640 |
Method for integrated circuit fabrication using pitch multiplication |
June 16, 2009 |
| Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substra |
| 7547617 |
Semiconductor device including container having epitaxial silicon therein |
June 16, 2009 |
| Methods for growing epitaxial silicon are provided. Methods for controlling bottom stacking fault propagation in epitaxial silicon are also provided. |
| 7547604 |
Method of forming a recessed gate structure on a substrate having insulating columns and removin |
June 16, 2009 |
| Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sac |
| 7547599 |
Multi-state memory cell |
June 16, 2009 |
| Floating-gate memory cells having a split floating gate facilitate decreased sensitivity to localized defects in the tunnel dielectric layer and/or the intergate dielectric layer. Such memory cells also permit storage of more than one bit per cell. Methods of the various embodiments |
| 7547579 |
Underfill process |
June 16, 2009 |
| A method and apparatus for underfilling a gap between a semiconductor die or device and a substrate, where the semiconductor die or device is electrically connected to the substrate so that an active surface of the semiconductor die is facing a top surface of the substrate with the gap |
| 7547559 |
Method for forming MRAM bit having a bottom sense layer utilizing electroless plating |
June 16, 2009 |
| The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. |
| 7547213 |
Memory modules and methods for manufacturing memory modules |
June 16, 2009 |
| Memory modules and methods for manufacturing memory modules are disclosed herein. In one embodiment, a memory module includes a substrate, a microelectronic device carried by the substrate, and a plurality of external contact pads operably coupled to the microelectronic device. The s |
| 7546435 |
Dynamic command and/or address mirroring system and method for memory modules |
June 9, 2009 |
| A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite surfaces being inter |
| 7546416 |
Method for substantially uninterrupted cache readout |
June 9, 2009 |
| A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring operations. The memory device outputs cached data from a first page while data from a second page is fetched into sense amp |
| 7545682 |
Erase block data splitting |
June 9, 2009 |
| A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into |
| 7545674 |
Flash memory with low tunnel barrier interpoly insulators |
June 9, 2009 |
| Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region a |
| 7545669 |
Resistive memory device |
June 9, 2009 |
| A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal, and a second terminal, and a control transistor having a gate, a first terminal, and a second terminal. The first terminal of |
| 7545388 |
Apparatus, method, and product for downscaling an image |
June 9, 2009 |
| An average filter or filters is used in line with the output of an interpolation filter to downscale an image. The interpolation filter upscales a source image or bitmap of pixels into an intermediate form and the average filter or filters downscales the intermediate form to a destin |
| 7545183 |
Integrated circuit comparator or amplifier |
June 9, 2009 |
| An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential |
| 7545009 |
Word lines for memory cells |
June 9, 2009 |
| Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Eac |
| 7544990 |
Scalable integrated logic and non-volatile memory |
June 9, 2009 |
| A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers. A c |
| 7544989 |
High density stepped, non-planar flash memory |
June 9, 2009 |
| A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column. The second plurality of memory cells are coupled to the first plurality of memory cells through a series connection of their |
| 7544987 |
High-k dielectric materials and processes for manufacturing them |
June 9, 2009 |
| High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting fi |
| 7544986 |
System including integrated circuit structures formed in a silicone ladder polymer layer |
June 9, 2009 |
| A method of forming integrated circuit structures, such as capacitors and conductive plugs, within contact openings formed in a photosensitive silicone ladder polymer (PVSQ) is disclosed. Contact openings with reduced striations and CD loss are formed in a photosensitive silicone lad |
| 7544984 |
Gettering using voids formed by surface transformation |
June 9, 2009 |
| One aspect of this disclosure relates to a memory device, comprising at least one gettering region, a memory array, a plurality of word lines and bit lines, and control circuitry. The gettering region is formed in a semiconductor substrate. The gettering region includes a precise arr |
| 7544921 |
Linear distributed pixel differential amplifier having mirrored inputs |
June 9, 2009 |
| A pixel circuit that partially incorporates an associated column amplifier into the pixel circuitry. By incorporating part of a mirrored amplifier into the pixel, noise from the pixel is reduced. |
| 7544624 |
Systems and methods for processing microfeature workpieces |
June 9, 2009 |
| Systems and methods for processing microfeature workpieces are disclosed herein. In one embodiment, the system comprises a processing chamber having a workpiece processing site configured to receive a microfeature workpiece and a main inlet through which a processing fluid can flow into |
| 7544622 |
Passivation for cleaning a material |
June 9, 2009 |
| A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove native oxide at the bottom of the contact with little effect on the BPSG, the contact is dipped in an etch retardant before be |
| 7544615 |
Systems and methods of forming refractory metal nitride layers using organic amines |
June 9, 2009 |
| A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum nitride barrier layer, on a substrate by using an atomic layer deposition process (a vapor deposition process that includes a plurality of deposition |
| 7544604 |
Tantalum lanthanide oxynitride films |
June 9, 2009 |
| Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be d |
| 7544596 |
Atomic layer deposition of GdScO3 films as gate dielectrics |
June 9, 2009 |
| The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of gadolinium oxide (Gd.sub.2O.sub.3) and scandium oxide (Sc.sub.2O.sub.3) acting as a single dielectric layer with a formula of GdScO.sub.3, and a method of fabricating such a dielectric layer, is described t |
| 7544592 |
Method for increasing etch rate during deep silicon dry etch |
June 9, 2009 |
| A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where differen |
| 7544584 |
Localized compressive strained semiconductor |
June 9, 2009 |
| One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded t |
| 7544563 |
Methods of forming a plurality of capacitors |
June 9, 2009 |
| The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node locations. Insulative material is deposited over the first material laterally about sidewalls of the projecting pillars, and is |
| 7544554 |
Methods of forming gatelines and transistor devices |
June 9, 2009 |
| The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segmen |
| 7544388 |
Methods of depositing materials over substrates, and methods of forming layers over substrates |
June 9, 2009 |
| The invention includes methods of utilizing supercritical fluids to introduce precursors into reaction chambers. In some aspects, a supercritical fluid is utilized to introduce at least one precursor into a chamber during ALD, and in particular aspects the supercritical fluid is util |
| 7542614 |
Image feature identification and motion compensation apparatus, systems, and methods |
June 2, 2009 |
| Apparatus, systems, and methods disclosed herein may estimate the magnitude of relative motion between a scene and an image capture device used to capture the scene. Some embodiments may utilize discrete cosine transform and/or Sobel gradient techniques to identify one or more blocks |
| 7542336 |
Architecture and method for NAND flash memory |
June 2, 2009 |
| A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at |
| 7542319 |
Chalcogenide glass constant current device, and its method of fabrication and operation |
June 2, 2009 |
| The invention is related to methods and apparatus for providing a two-terminal constant current device, and its operation thereof. The invention provides a constant current device that maintains a constant current over an applied voltage range of at least approximately 700 mV. The in |
| 7541963 |
Variable quantization ADC for image sensors |
June 2, 2009 |
| An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled s |
| 7541871 |
Operational transconductance amplifier (OTA) |
June 2, 2009 |
| Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include a current-mirror OTA and a folded-cascode OTA. In one embodiment, the self-biasing cascode current mirror is an optional aspec |
| 7541851 |
Control of a variable delay line using line entry point to modify line power supply voltage |
June 2, 2009 |
| Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small |
| 7541825 |
Isolation circuit |
June 2, 2009 |
| The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first transistor having its source connected to a first terminal, wherein the first terminal connects a supply voltage to the sourc |
| 7541658 |
Optically interactive device package array |
June 2, 2009 |
| An image sensor package and methods for simultaneously fabricating a plurality of such packages. A layer of barrier material comprising a matrix of raised walls is formed around chip attachment areas located in an array on a carrier substrate to create chip cavities. Image sensor chi |
| 7541648 |
Electrostatic discharge (ESD) protection circuit |
June 2, 2009 |
| An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs) each with a floating base and a metal oxide semiconductor (MOS) field transistor with a floating body is disclosed. The three |
| 7541635 |
Semiconductor fabrication using a collar |
June 2, 2009 |
| In one embodiment, a method includes selectively depositing a collar material between a number of memory containers. The collar material along a side of a first memory container of the number of memory containers is in contact with the collar material along a side of a second memory |
| 7541632 |
Relaxed-pitch method of aligning active area to digit line |
June 2, 2009 |
| According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at least two drains defining a first axis. The memory device further comprises at least two substantially parallel word lines, at |
