| Patent Number |
Title Of Patent |
Date Issued |
| 7557013 |
Methods of forming a plurality of capacitors |
July 7, 2009 |
| A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node |
| 7557006 |
Methods of forming field effect transistors |
July 7, 2009 |
| A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided laterally between the mass of material and the semiconductive material. The space comprises an outermost portion and a portion |
| 7557002 |
Methods of forming transistor devices |
July 7, 2009 |
| Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may |
| 7557001 |
Semiconductor processing methods |
July 7, 2009 |
| The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or |
| 7556897 |
Methods of forming reticles |
July 7, 2009 |
| The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes provision of a reticle substrate having a defined main-field region and a defined boundary region. The substrate has a relatively |
| 7555358 |
Process and method for continuous, non lot-based integrated circuit manufacturing |
June 30, 2009 |
| A method for continuous, non lot-based manufacturing of integrated circuit (IC) devices of the type to each have a unique fuse identification (ID) includes: reading the fuse ID of each of the IC devices; advancing multiple lots of the IC devices through, for example, a test step in the |
| 7554858 |
System and method for reducing pin-count of memory devices, and memory device testers for same |
June 30, 2009 |
| Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are conne |
| 7554852 |
Method of erasing flash memory with pre-programming memory cells only in the presence of a cell |
June 30, 2009 |
| Some embodiments include converting a plurality of memory cells into a first logic state, and converting the plurality of memory cells into a second logic state only if a leakage occurs after the plurality of memory cells are converted into the first logic state. Other embodiments in |
| 7554846 |
Select gate transistors and methods of operating the same |
June 30, 2009 |
| Memory arrays, methods and cells are disclosed, such as those involving a floating gate memory array having a plurality of transistors arranged in a plurality of rows and columns, wherein each column comprises a string of the plurality of transistors coupled in series. Each such transist |
| 7554829 |
Transmission lines for CMOS integrated circuits |
June 30, 2009 |
| Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present i |
| 7554589 |
Redundancy in column parallel or row architectures |
June 30, 2009 |
| A column circuitry architecture for an imager includes redundant column or row circuits. The column or row circuitry includes a number of redundant column or row circuits. Each column or row circuit include circuitry for controllably coupling the column or row circuit to one of plural si |
| 7554375 |
Delay line circuit |
June 30, 2009 |
| Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay line to synchronize two clock signals. |
| 7554200 |
Semiconductor devices including porous insulators |
June 30, 2009 |
| Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced die |
| 7554171 |
Semiconductor constructions |
June 30, 2009 |
| The invention includes a method of forming a planarized surface over a semiconductor substrate. A substrate is provided which includes a memory array region and a peripheral region proximate the memory array region. The memory array region has a higher average elevational height than the |
| 7554161 |
HfAlO.sub.3 films for gate dielectrics |
June 30, 2009 |
| A dielectric film containing HfAlO.sub.3 and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO.sub.2. A gate dielectric is formed by atomic layer deposition employing a hafnium sequ |
| 7554142 |
Ultrashallow photodiode using indium |
June 30, 2009 |
| The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to decrease transient enhanced diffusion effects, minimize fixed pattern noise and fill factor loss. |
| 7554071 |
Method and apparatus providing pixel array having automatic light control pixels and image captu |
June 30, 2009 |
| A pixel array uses two sets of pixels to provide accurate exposure control. One set of pixels provide continuous output signals for automatic light control (ALC) as the other set integrates and captures an image. ALC pixels allow monitoring of multiple pixels of an array to obtain sa |
| 7553770 |
Reverse masking profile improvements in high aspect ratio etch |
June 30, 2009 |
| A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of amorphous carbon is deposited over a substrate. An inorganic hard mask is deposited on the amorphous carbon followed by a |
| 7553735 |
Scalable high performance non-volatile memory cells using multi-mechanism carrier transport |
June 30, 2009 |
| A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a vertical embodimen |
| 7553699 |
Method of fabricating microelectronic devices |
June 30, 2009 |
| Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such method includes forming a plurality of through holes in a substrate with the through holes arranged in arrays, and attaching a plurality of singulated microel |
| 7553697 |
Multiple chip semiconductor package |
June 30, 2009 |
| A semiconductor device package and method of fabricating the same are disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a |
| 7553688 |
Methods for packaging image sensitive electronic devices |
June 30, 2009 |
| The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a barrier of transfer |
| 7553472 |
Nanotube forming methods |
June 30, 2009 |
| A nanotube forming method includes growing a plurality of nanotubes to an intermediate length that is deterministic of nanotube intrinsic conductivity. Individual nanotubes exhibit an effective conductivity, which varies among the plurality of nanotubes. The method includes completin |
| 7552364 |
Diagnostic and managing distributed processor system |
June 23, 2009 |
| A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a management system by which computer users can accurately gauge the health of their computer. The network of microcontrollers |
| 7552274 |
Flash memory architecture with separate storage of overhead and user data |
June 23, 2009 |
| A flash memory system segregates overhead data from user data so that overhead data may be addressed, programmed and erased independently from user data. The non-volatile memory medium of a flash memory system is mapped into a plurality of separate and separately addressable memory b |
| 7551510 |
Memory block reallocation in a flash memory device |
June 23, 2009 |
| A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline |
| 7551509 |
Power circuits for reducing a number of power supply voltage taps required for sensing a resisti |
June 23, 2009 |
| A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are g |
| 7551481 |
User configurable commands for flash memory |
June 23, 2009 |
| A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of the initialization routine. If the boot data includes a reconfigured command, that command is loaded into the register. A |
| 7551467 |
Memory device architectures and operation |
June 23, 2009 |
| Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional |
| 7551466 |
Bit line coupling |
June 23, 2009 |
| The invention provides methods and apparatus. Alternate bit-line pairs of a memory device are concurrently selected. Each bit-line pair has one bit line formed at a first vertical level and one adjacent bit line formed at a second vertical level different than the first vertical level. |
| 7550985 |
Methods of testing memory devices |
June 23, 2009 |
| A testing apparatus, system and method for testing computer memory modules are disclosed. The apparatus includes a motherboard having a processor and at least one resident memory socket fixed to the motherboard. A remote memory socket is provided and located a distance from the resident |
| 7550848 |
Semiconductor constructions comprising particle-containing materials |
June 23, 2009 |
| The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semicondu |
| 7550847 |
Packaged microelectronic devices and methods for packaging microelectronic devices |
June 23, 2009 |
| Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the firs |
| 7550824 |
Low k interconnect dielectric using surface transformation |
June 23, 2009 |
| Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement |
| 7550818 |
Method of manufacture of a PCRAM memory cell |
June 23, 2009 |
| The invention provides a method of forming a resistance variable memory element and the resulting element. The method includes forming an insulating layer having an opening therein; forming a metal containing layer recessed in the opening; forming a resistance variable material in th |
| 7550816 |
Filled trench isolation structure |
June 23, 2009 |
| A method for depositing a dielectric in a trench on a semiconductor substrate is provided. The dielectric is deposited by using an HDP-CVD system and performing a deposition of first and second layers of dielectric material. A first inert gas is utilized during the deposition of the |
| 7550762 |
Isolation circuit |
June 23, 2009 |
| An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the |
| 7550380 |
Electroless plating of metal caps for chalcogenide-based memory devices |
June 23, 2009 |
| A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming |
| 7550345 |
Methods of forming hafnium-containing materials |
June 23, 2009 |
| The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is provided, and first reaction conditions are utilized to form hafnium-containing seed material in a desired crystalline phase and or |
| 7550341 |
High density stepped, non-planar flash memory |
June 23, 2009 |
| A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column. The second plurality of memory cells are coupled to the first plurality of memory cells through a series connection of their |
| 7550340 |
Silicon rich barrier layers for integrated circuit devices |
June 23, 2009 |
| Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich b |
| 7550339 |
Memory device with high dielectric constant gate dielectrics and metal floating gates |
June 23, 2009 |
| A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are |
| 7550315 |
Method for fabricating semiconductor package with multi-layer die contact and external contact |
June 23, 2009 |
| A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a |
| 7549143 |
Method and device for checking lithography data |
June 16, 2009 |
| Devices and methods are provided that include advantages such as the ability to identify sizes, shapes and locations of frequently unwanted additional features that occur as a result of photolithographic interference. The additional feature information is obtained through use of simu |
| 7549142 |
Method and device for checking lithography data |
June 16, 2009 |
| Devices and methods are provided that include advantages such as the ability to identify sizes, shapes and locations of frequently unwanted additional features that occur as a result of photolithographic interference. The additional feature information is obtained through use of simu |
| 7549033 |
Dual edge command |
June 16, 2009 |
| A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on |
| 7549011 |
Bit inversion in memory devices |
June 16, 2009 |
| Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the source, the set bits associated with data are tabulated. If the total number of set bits exceeds more than half of the total b |
| 7548667 |
Optical integrated circuit |
June 16, 2009 |
| The present technique relates to a device including an optical integrated circuit amplifier and another type of optical integrated circuit. The optical integrated circuit amplifiers and other optical integrated circuits are coupled together through optical paths. The optical integrat |
| 7548483 |
Memory device and method having multiple address, data and command buses |
June 16, 2009 |
| A dynamic random access memory ("DRAM") device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The |
| 7548459 |
Method, apparatus, and system providing adjustable memory page configuration |
June 16, 2009 |
| A method, apparatus and system providing a memory device having an array of cells which may be selectively designated for either error correction code use or redundancy cell use. |
