| Patent Number |
Title Of Patent |
Date Issued |
| RE43665 |
Reading non-volatile multilevel memory cells |
September 18, 2012 |
| Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a |
| RE41441 |
Output buffer having inherently precise data masking |
July 13, 2010 |
| A maskable data output buffer includes an output stage receiving data signals from a data coder. The signals output from the data coder are normally complementary data signals corresponding to complementary data input signals. However, in response to receiving a mask signal, the data |
| RE41340 |
Pinned photodiode photodetector with common buffer transistor and binning capability |
May 18, 2010 |
| .[.A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that |
| RE40995 |
Multi-element resistive memory |
November 24, 2009 |
| A memory device.Iadd., and methods relating thereto, .Iaddend.having memory cells in which .[.a single.]. .Iadd.an .Iaddend.access transistor controls the grounding of at least two .[.storage.]. .Iadd.resistive memory .Iaddend.elements.[., such as resistive storage elements,.]. for |
| RE40842 |
Memory elements and methods for making same |
July 14, 2009 |
| Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as |
| RE40819 |
Semiconductor device with improved bond pads |
July 7, 2009 |
| A semiconductor device with improved bond pads. The semiconductor device includes bond pads electrically connected to an active circuit in the device and openings formed in the bonding surface of the bond pads. The opening(s) may include recesses extending partially into the bonding |
| RE40790 |
Method for making electrical contact with an active area through sub-micron contact openings and |
June 23, 2009 |
| A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive runners on a semiconductor wafer; (b) providing insulative spacers on the sides of the conductive runners wherein adjacent spacers |
| RE40623 |
Method and apparatus for identifying integrated circuits |
January 20, 2009 |
| An integrated circuit and method for identifying same is described. The integrated circuit includes a programmable identification circuit for storing electronic identification information. The integrated circuit also includes an optical identification mark displaying a machine-readab |
| RE40490 |
Method and apparatus for programmable field emission display |
September 9, 2008 |
| A method and apparatus for programmable field emission display comprising an array of cathodoluminescent elements. Each cathodoluminescent element in the array is responsive to separate select signals to cause light to be emitted from said display at a location in the array corresponding |
| RE40137 |
Methods for forming integrated circuits within substrates |
March 4, 2008 |
| .[.The invention includes methods for forming integrated circuits within substrates, and embedded circuits. In one aspect, the invention includes a method of forming an integrated circuit within a substrate comprising: a) providing a recess in a substrate; b) printing an antenna within t |
| RE40114 |
Tungsten silicide (WSIX) deposition process for semiconductor manufacture |
February 26, 2008 |
| A semiconductor manufacturing process for depositing a tungsten silicide film on a substrate includes deposition of a tungsten silicide nucleation layer on the substrate using a (CVD) process with a silane source gas followed by deposition of the tungsten silicide film with a dichlor |
| RE40061 |
Multi-chip stacked devices |
February 12, 2008 |
| A multiple stacked die device is disclosed that contains up to four dies and does not exceed the height of current single die packages. Close-tolerance stacking is made possible by a low-loop-profile wire-bonding operation and thin-adhesive layer between the stacked dies. |
| RE39768 |
VCC pump for CMOS imagers |
August 14, 2007 |
| A CMOS imaging device which includes a charge pump connected to one or more of a reset gate, transfer gate and row select gate of sensor cells and provides gate control signals which give the imaging device an increased dynamic range charge capacity while minimizing signal leakage. A |
| RE39665 |
Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemi |
May 29, 2007 |
| An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The present invention develops the container capacitor by etching an opening (or contact opening) into a low etch rate oxide. The contact opening is used as a f |
| RE39547 |
Method and apparatus for endpointing mechanical and chemical-mechanical polishing of substrates |
April 3, 2007 |
| An apparatus and method for stopping mechanical and chemical-mechanical polishing of a substrate at a desired endpoint. In one embodiment, a polishing machine has a platen, a polishing pad positioned on the platen, and a polishing medium located at a planarizing surface of the polishing |
| RE39413 |
Low friction polish-stop stratum for endpointing chemical-mechanical planarization processing of |
November 28, 2006 |
| The present invention is a semiconductor wafer that enhances polish-stop endpointing in chemical-mechanical planarization processes. The semiconductor wafer has a substrate with a device feature formed on the substrate, a stratum of low friction material positioned over the substrate |
| RE39195 |
Polishing pad refurbisher for in situ, real-time conditioning and cleaning of a polishing pad us |
July 18, 2006 |
| A pad refurbisher that provides in situ, real-time conditioning and/or cleaning of a polishing surface on a polishing pad used in chemical-mechanical polishing of a semiconductor wafer and other microelectronic substrates. The pad refurbisher has a body adapted for attachment to a wa |
| RE39194 |
Method and apparatus for controlling planarizing characteristics in mechanical and chemical-mech |
July 18, 2006 |
| A method and apparatus for mechanical and/or chemical-mechanical planarization of microelectronic substrates. In one embodiment, an apparatus for controlling the planarizing characteristics of a microelectronic substrate has a carrier that may be positioned with respect to a polishin |
| RE39126 |
Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs |
June 13, 2006 |
| A method for forming conductive plugs within an insulation material is described. The inventive process results in a plug of a material such as tungsten which is more even with the insulation layer surface than conventional plug formation techniques. Conventional processes result in |
| RE38956 |
Data compression circuit and method for testing memory devices |
January 31, 2006 |
| A test circuit detects defective memory cells in a memory device. The test circuit includes a test mode terminal adapted to receive a test mode signal. An error detection circuit includes a plurality of inputs and an output, each input coupled to some of the plurality of memory cells. Th |
| RE38955 |
Memory device having a relatively wide data bus |
January 31, 2006 |
| An architecture for a wide data path in a memory device formed in a semiconductor substrate includes an array of memory cells is formed in an array region of the substrate, the array including a plurality of memory cells arranged in rows and columns. A plurality of complementary pairs of |
| RE38903 |
Method and apparatus for generating a pulse |
November 29, 2005 |
| A circuit for generating a pulse with minimal delay after receiving a trigger signal includes a passgate, a gating circuit, and a reset circuit. The passgate is enabled by control signals received at the gating circuit having a trigger signal as one of the control signals. The trigger si |
| RE38685 |
Data-output driver circuit and method |
January 11, 2005 |
| A drive circuit includes drive input and output terminals, a supply terminal, a drive transistor, and a drive-control circuit. The drive transistor includes a control terminal, a first transistor terminal coupled to the drive output terminal, and a second transistor terminal coupled |
| RE38109 |
Block write circuit and method for wide data path memory device |
May 6, 2003 |
| A block write circuit in a memory device having a wide internal data path performs block write and data masking functions. The memory device includes a plurality of data terminals adapted to receive respective data signals, and a plurality of array groups each including a plurality of |
| RE38049 |
Optimized container stacked capacitor dram cell utilizing sacrificial oxide deposition and chemi |
March 25, 2003 |
| An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The present invention develops the container capacitor by etching an opening (or contact opening) into a low etch rate oxide. The contact opening is used as a form |
| RE37997 |
Polishing pad with controlled abrasion rate |
February 18, 2003 |
| A polishing pad is provided, having its face shaped to produce controlled nonuniform removal of material from a workpiece. Non-uniformity is produced as a function of distance from the pad's rotational axis (the working radius). The pad face is configured with both raised, contact re |
| RE37865 |
Semiconductor electrical interconnection methods |
October 1, 2002 |
| A semiconductor metallization processing method for multi-level electrical interconnection includes: a) providing a base insulating layer atop a semiconductor wafer; b) etching a groove pathway into the base layer; c) providing a first contact through the base layer to the area to which |
| RE37611 |
Non-volatile memory system having internal data verification test mode |
March 26, 2002 |
| A memory system including means for verifying the contents of a memory cell contained in a memory array to determine if a shift in the threshold voltage level has occurred. The memory system is placed into a test mode of operation in which an internal program or erase verify operation is |
| RE37505 |
Stacked capacitor construction |
January 15, 2002 |
| A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reac |
| RE37396 |
Semiconductor wire bonding method |
October 2, 2001 |
| An improved method for teaching the location of a bond site on a selected lead finger of a semiconductor leadframe during a wire bonding process is provided. Initially, the location of the lateral edges and terminal edge of a tip portion of the lead finger is sensed by an automated visio |
| RE37158 |
High performance sub-micron P-channel transistor with germanium implant |
May 1, 2001 |
| Implantation of germanium (45) into a PMOS buried channel to permits the enhancement implant profile (to 45) to be made more shallow. The shallow profile will reduce or eventually solve P-channel buried channel-induced short channel effects and enable further decrease in device length to |
| RE37104 |
Planarization of a gate electrode for improved gate patterning over non-planar active area isola |
March 20, 2001 |
| The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon |
| RE36952 |
One time programmable fully-testable programmable logic device with zero power and anti-fuse cel |
November 14, 2000 |
| There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the |
| RE36843 |
Polymer-lithium batteries and improved methods for manufacturing batteries |
August 29, 2000 |
| Improved polymer batteries and improved methods of manufacturing such polymer batteries are provided. One improved method of manufacture involves the formation of a laminated array structure that includes a number of individual battery cells. After formation of the laminated array th |
| RE36821 |
Wordline driver circuit having a directly gated pull-down device |
August 15, 2000 |
| The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The drivin |
| RE36786 |
Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sid |
July 18, 2000 |
| The present invention develops a container capacitor by forming a first insulative layer over conductive word lines; forming an opening between neighboring conductive word lines; forming a conductive plug between neighboring parallel conductive word lines; forming a planarized blanke |
| RE36735 |
Self-aligned low resistance buried contact process |
June 13, 2000 |
| A buried contact is formed in a substrate implantation of phosphorous or arsenic through a window cut into the insulating silicon oxide layer and a superimposed thin silicon layer. The photoresist used to etch the window is cut back a limited amount prior to implantation. The peripheral |
| RE36644 |
Tapered via, structures made therewith, and methods of producing same |
April 4, 2000 |
| After formation of the storage poly in a stacked capacitor DRAM, the oxide 1 layer is partially etched to leave a thick oxide deposition in the area of the future bit line contact, upon which the cell poly is deposited, followed by oxide 2 and then a poly or nitride layer. A mask and etc |
| RE36613 |
Multi-chip stacked devices |
March 14, 2000 |
| A multiple stacked die device is disclosed that contains up to four dies and does not exceed the height of current single die packages. Close-tolerance stacking is made possible by a low-loop-profile wire-bonding operation and thin-adhesive layer between the stacked dies. |
| RE36518 |
Method for making electrical contact with an active area through sub-micron contact openings and |
January 18, 2000 |
| A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive runners on a semiconductor wafer; (b) providing insulative spacers on the sides of the conductive runners wherein adjacent spacers |
| RE36469 |
Packaging for semiconductor logic devices |
December 28, 1999 |
| A logic module design is disclosed which incorporates an unencapsulated wafer section or sections. The disclosed module is an improvement over previous designs in that it is less expensive and easier to manufacture due to the reduced number of components and the complexity of the com |
| RE36325 |
Directly bonded SIMM module |
October 5, 1999 |
| A leadframe interconnect package is tape automated bond (TAB) bonded to circuitry on the chip and which provides a circuit connection for subsequent connection to a printed circuit board. The encapsulated chips will replace both the leadframe and printed circuit board (electrical onl |
| RE36305 |
Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer |
September 14, 1999 |
| A method for fabricating submicron lines over a semiconductor material by creating a narrow hard mask over the material using a narrow void-producing process. The narrow void is thus used as a mask to form lines that are narrower than those that can be produced by current lithography |
| RE36264 |
Read circuit for accessing dynamic random access memories (DRAMs) |
August 3, 1999 |
| DRAM read accessing circuitry having two parallel connected control lines, one of which includes a level translator stage and the other of which includes an enable gate. Both the level translator stage and the enable gate are connected to receive 0.0 to 3 volt small logic swings from out |
| RE36180 |
Simultaneous read and refresh of different rows in a DRAM |
April 6, 1999 |
| A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells includes M rows and N columns of memory cells, each row being arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 |
| RE36087 |
Method and system for decoupling inoperative passive elements on a semiconductor chip |
February 9, 1999 |
| The present invention teaches a method and system for disconnecting shorted decoupling capacitors, wherein a semiconductor chip having a plurality of redundant decoupling capacitors. Each of the capacitors is coupled, by means of a link, to a bus having a predetermined voltage. Each link |
| RE36050 |
Method for repeatable temperature measurement using surface reflectivity |
January 19, 1999 |
| A method is disclosed for continuously measuring the temperature of a semiconductor substrate in a chamber is disclosed. The first step of the method involves providing a substantially clean semiconductor substrate having a layer a reflective surface thereon into a chamber. A film is |
| RE36024 |
Electrostatic discharge protection circuit for semiconductor device |
January 5, 1999 |
| An ESD protection circuit (38) for a MOS device uses at least one electrically floating-base N+P-N+ transistor (43) connected between a metal bonding pad (40) and ground. The electrically floating base region (44) of each transistor is formed by a thin oxide region deposited over a s |
| RE35847 |
Self-terminating data line driver |
July 14, 1998 |
| The invention is a self-terminating helper flip-flop buffer circuit pertinent to a dynamic random access memory (DRAM) or static random access memory (SRAM) device. The invention turns off a device which is sourcing current to pull the data line low. The device is turned off when the |
| RE35828 |
Anti-fuse circuit and method wherein the read operation and programming operation are reversed |
June 23, 1998 |
| The invention features a circuit wherein a serially connected transistor and anti-fuse element are biased for current to flow in a first direction or the current flows in the first direction during a programming operation and biased for a current to flow in a second direction or current |
