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Matra MHS Patents
Assignee:
Matra MHS
Address:
Nantes, FR
No. of patents:
11
Patents:












Patent Number Title Of Patent Date Issued
5880600 Device for interfacing logic signals from the LLL level to the TTL and CMOS level March 9, 1999
A device for interfacing from the LLL level to the TTL and CMOS level that comprises, in cascade, a first and a second amplifier-inverter and a shaping circuit delivering an inverted logic signal at the TTL level. A power inverter-amplifier circuit receives the inverted logic signal at t
5789941 ECL level/CMOS level logic signal interfacing device August 4, 1998
An ECL level/CMOS level logic signal interfacing device includes, connected in cascade, a circuit for generating an in-phase relationship with an ECL level input signal, a threshold inverter circuit receiving the in-phase signal at an inverter input and delivering an inverted in-phase si
5754135 Analog-to digital conversion device having a standby mode May 19, 1998
This analog-digital conversion device comprises switching means (CS) having two close and centered triggering thresholds; a NOR logic gate (PL) which, when the conversion device is not being used, receives a standby command signal and delivers a zero digital output signal (NOUT) imposed
5679594 Method of fabricating a read only memory in MOS technology, and memory thus obtained October 21, 1997
A method of fabricating a read only memory consisting of a matrix of arrays of enhancement-mode or depletion-mode programmed MOS transistors that consists, on a silicon substrate (SU) of a first conduction type, in defining by masking, retrograde wells of the same conduction type as that
5666388 Clock recovery circuit with matched oscillators September 9, 1997
A clock recovery circuit comprises first and second voltage-controlled oscillators having identical characteristics. The first oscillator is incorporated into a frequency synthesis loop in such a way as to oscillate, in response to a first control voltage, at a frequency equal to a r
5604455 Transition detection device generating a variable-duration pulse February 18, 1997
A transition detection device, generating a variable-duration pulse, such as an enable signal for the input circuits of a CMOS static memory circuit, receiving an input signal that includes a delay circuit of determined delay value, making it possible to generate a delayed enable sig
5602512 Comparator of phase between a digital signal and a clock signal, and corresponding phase locked February 11, 1997
A comparator of phase between a digital signal and a clock signal adapted for the construction of a phase locked loop in integrated circuit form, that includes a first channel formed by a flip-flop and an exclusive OR gate, and a second channel formed by a second exclusive OR gate and a
5541533 Output circuit for an TTL-CMOS integrated circuit July 30, 1996
An output circuit for a TTL-CMOS integrated circuit that comprises an output stage with two P MOS and N MOS transistors in parallel, which are connected in cascade with an N MOS enabling transistor between the power supply and the reference voltages. The output stage connected by means o
5441893 Method for monitoring the boron content of borophosphosilicate August 15, 1995
A method for monitoring the boron content of the borophosphosilicate, BPSG. The BPSG is obtained by the oxidation of silane, of diborane and of phosphine in a reactor, starting with a first, diborane/silane gas mixture and a second, phosphine/silane gas mixture by monitoring the ratio
5378309 Method for controlling the etching profile of a layer of an integrated circuit January 3, 1995
The invention concerns a process for slope etching a layer of an integrated circuit. The layer to be etched is coated with a masking photoresist layer. The process consists of jointly performing a passivation of the etching flank of the layer to be etched and a nonisotropic erosion of th
5377137 Read-protected semiconductor program memory December 27, 1994
A read protected semi-conductor program memory that can be used for protection of read-only memories built in microhandler of microcomputers comprising a first program memory area intended for storing the program data and a second encryption memory area intended for storing encryption

 
 
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