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Marvell World Trade Ltd Patents
Marvell World Trade Ltd
St. Michael, BB
No. of patents:

1 2 3 4 5 6 7 8 9

Patent Number Title Of Patent Date Issued
8588768 RSSI estimation in multi-technology communication terminals November 19, 2013
A method used in a receiver includes measuring first Received Signal Strength Indications (RSSIs) in respective first communication channels, which are located in a given frequency band and which each have a first channel bandwidth. Based on the first RSSIs, second RSSIs are computed
8588144 Access point with simultaneous downlink transmission of independent data for multiple client sta November 19, 2013
A wireless network device includes modulation modules, each configured to receive a data stream and modulate the data stream to generate a modulated data stream. A matrix module generates a multiplexing matrix based on channel conditions between the wireless network device and each o
8583981 Concatenated codes for holographic storage November 12, 2013
Systems and methods for constructing concatenated codes for data storage channels, such as holographic storage channels, are provided. The concatenated codes include an outer BCH code and an inner iteratively decodable code, such as an LDPC code or turbo code. The correction power an
8583893 Metadata management for virtual volumes November 12, 2013
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, manage metadata for virtual volumes. In some implementations, a method and system include defining multiple metadata blocks in a persistent storage, including information that links a v
8583857 Method and system for object-oriented data storage November 12, 2013
In accordance with the present invention, data may be written and read differently in accordance with their attributes, which may include, inter alia, critical vs. non-critical data, streaming vs. non-streaming media, confidential vs. non-confidential, or read or write speed requirements
8582768 Recovery from decryption errors in a sequence of communication packets November 12, 2013
A method in a receiver includes receiving from a transmitter a sequence of communication packets, which carry data encrypted with an encryption scheme. The encryption scheme depends on a counter value that is incremented independently by each of the transmitter and the receiver. Atte
8582707 Programmable universal asynchronous receiver/transmitter (UART) based on reference frequency November 12, 2013
In one embodiment, a method includes determining pre-calculated information. The pre-calculated information is used to determine a counter pattern for a reference clock. The counter pattern include, for at least one data bit, a number of reference clock cycles of the reference clock
8582461 Analytical computation of cubic metric November 12, 2013
A method includes determining attributes of multiple Code-Division Multiple Access (CDMA) signals, which are to be superimposed to form a composite CDMA signal for transmission by a wireless transmitter. A predefined analytical formula, which computes a Cubic Metric of the composite
8582332 Dual output DC-DC charge pump regulator November 12, 2013
An apparatus includes a first switch coupled to a first voltage reference and a second switch coupled to a second voltage reference. A third switch is coupled to a first terminal of a first capacitor and a first terminal of a second capacitor. A fourth switch is coupled to a second termi
8581765 Low-memory-usage arbitrary waveform representation or generation November 12, 2013
This disclosure describes techniques and apparatuses for low-memory-usage arbitrary waveform representation or generation. These techniques and/or apparatuses enable representation and/or generation of arbitrary waveforms using less memory than many current techniques, thereby reduci
8581762 Continuous time sigma-delta ADC with embedded low-pass filter November 12, 2013
A filtering analog to digital converter (ADC) includes an integrator receiving at its input an analog input signal. A filtering capacitor at the input of the integrator filters out a large portion of out-of-band interferers in the analog input signal. The integrator produces an output
8578248 Adaptive systems and methods for storing and retrieving data to and from memory cells November 5, 2013
Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data q
8576954 Method and apparatus of cross-correlation November 5, 2013
Briefly, a method and apparatus to calculate cross-correlation values of complex binary sequences are provided. The apparatus may include a transformation unit and a cross-correlator. The cross-correlator may include a cross-correlation controller to provide, based on a type bit and
8576759 Partial power save mode for access points during device discovery November 5, 2013
An access point includes a beacon module and a control module. The access point transmits a beacon during a beacon interval. The beacon module determines a first portion of the beacon interval and a second portion of the beacon interval. The access point operates in a normal mode during
8575968 Fast power up comparator November 5, 2013
A circuit method includes periodically increasing a tail current of a differential stage of a comparator to periodically power on the differential stage to a power-on state, and periodically decreasing the tail current of the differential stage to periodically power down the differen
8572416 Low power computer with main and auxiliary processors October 29, 2013
A processing device including first processors, second processors, a first chipset, and a second chipset. The first chipset is in communication with the first processors via a first bus. The second chipset is in communication with the first chipset via a second bus and is directly co
8572309 Apparatus and method to protect metadata against unexpected power down October 29, 2013
A system includes first memory configured to store first metadata to associate logical addresses with physical addresses. Second memory is configured to include the physical addresses, to store first data based on the physical addresses, and to store portions of the first metadata wh
8571591 Coexistence support for multi-channel wireless communications October 29, 2013
Systems and techniques relating to wireless communications are described. A described technique includes monitoring a group of wireless channels that are useable by at least a first wireless communication device for wireless communications, receiving one or more beacon signals from one o
8571479 Short-range wireless communication October 29, 2013
The present specification describes techniques and apparatus that enable wireless devices to communicate effectively at short ranges. In one implementation, the transmit power of a transmitting device is reduced to permit a receiving device to demodulate a signal.
8570925 Systems and methods for reducing power consumption in wireless devices October 29, 2013
A method for reducing power consumption in wireless devices includes establishing a wireless link between a local device and a remote device and sending a message to the remote device across the wireless link. The message may specify a communication schedule. Communications between the
8570887 Analog bias control for packet communication systems October 29, 2013
Apparatus having corresponding methods and non-transitory computer-readable media comprise an amplifier configured to amplify signals according to a bias current, wherein the signals represent packets of data; a packet module configured to recover the packets of data from the signals
8570681 Dual channel HDD systems and methods October 29, 2013
A hard disk drive system includes a first channel module and a second channel module. The first channel module is configured to receive a first data from or transfer the first data to a first amplifier module of a hard disk assembly when reading from or writing to a first surface of a
8570438 Automatic adjustments for video post-processor based on estimated quality of internet video cont October 29, 2013
A system including a quality estimation module configured to estimate a visual quality of video content based on data from a decoder module. The system further including a settings database configured to store a plurality of predetermined settings. The settings database outputs at le
8570199 Digital to analog converter circuits and methods October 29, 2013
The present disclosure provides for improved DAC circuits and methods. In one embodiment, a digital-to-analog converter receives a digital signal and outputs a first analog output signal corresponding to the digital signal. A current buffer receives the first analog output signal and
8566664 System and method for correcting errors in non-volatile memory using products codes October 22, 2013
A product code encoder for non-volatile (NV) memory includes a first encoder that encodes data in codewords in a first dimension that is stored in the NV memory. The product code encoder also includes a second encoder that encodes data in codewords in a second dimension that is store
8565349 Frequency and Q-factor tunable filters using frequency translatable impedance structures October 22, 2013
A system includes an input node, a frequency translatable impedance (FTI) filter, and a radio frequency (RF) downconverter module. The input receives an input signal having first and second components. The FTI filter filters the second components. The RF downconverter module receives
8565183 Method and apparatus for preventing interference between collocated transceivers October 22, 2013
A network device including a first transceiver, a second transceiver, and a control module. The first transceiver communicates with a first network device on a first channel using a first wireless communication standard. The second transceiver communicates with a second network device on
8564342 Reference clock compensation for fractional-N phase lock loops (PLLs) October 22, 2013
In one embodiment, a method includes determining a phase difference between a reference clock and a feedback clock in even and odd cycles for a phase lock loop (PLL). The even and odd cycles are alternating clock periods. A delta value based on the phase difference is determined. The
8564091 Die-to-die electrical isolation in a semiconductor package October 22, 2013
Some of the embodiments of the present disclosure provide a semiconductor package comprising a first die; a second die; and an inductor arrangement configured to inductively couple the first die and the second die while maintaining electrical isolation between active circuit components o
8301099 Method and apparatus for downconverting a plurality of frequency modulated signals from a carrie October 30, 2012
Circuits, systems, and methods are disclosed for controlling multiple antenna receive paths in a wireless communication device. In some embodiments, the circuit may include a pair of receiving antennas, a first receive path including a VCO coupled to receive a PLL signal and a first
8301098 System and transceiver clocking to minimize required number of reference sources in multi-functi October 30, 2012
A system comprises a first clock module configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). A global position system (GPS) module is configured to receive the first clock reference. An integrated circuit for a cellular tran
8299763 Digital low dropout regulator October 30, 2012
A circuit includes a regulator. The regulator includes first and second inductors and first and second arrays of switches. An output of the second inductor is connected to an output of the first inductor. The first array of switches is configured to receive an input voltage and is co
8296555 Preloader October 23, 2012
This disclosure describes techniques and/or apparatuses for reducing the total time used to boot up a computer and load applications onto the computer.
8295110 Processor instruction cache with dual-read modes October 23, 2012
A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second inst
8294248 Chip on leads October 23, 2012
Described herein are microelectronic packages including a plurality of bonding fingers and multiple integrated circuit chips, at least one integrated circuit chip being mounted onto the bonding fingers. According to various embodiments of the present invention, mounting the integrated
8284322 Shared memory multi video channel display apparatus and methods October 9, 2012
A shared memory video processor including signal processing circuitry. The signal processing circuitry may enable a noise reducer and a de-interlacer to share access to field buffers in a memory device to store various field lines. Some of the stored field lines may also be shared wi
8281191 Fully-buffered dual in-line memory module with fault correction October 2, 2012
A memory circuit including a logic circuit, content addressable memory, and a multiplexer. The logic circuit is configured to output a first address. The content addressable memory is configured to i) receive the first address and ii) output a substitute address and a match signal if
8279966 Symbol-level combining for multiple input multiple output (MIMO) systems with hybrid automatic r October 2, 2012
Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The symbols of the received signal vectors are combined, forming a combined rece
8279963 Data symbol mapping for multiple-input multiple-output hybrid automatic repeat request October 2, 2012
A system includes an encoding module, a symbol selection module, a subcarrier selection module, and a mapping module. The encoding module receives symbols for transmission over K subcarriers and T antennas, encodes the symbols using a space time code, and generates space time coded (
8278861 External disturbance detection system and method for two-phase motor control systems October 2, 2012
A system includes a power control module, a period determination module, and a control module. The power control module controls current through stator coils of a motor to rotate a rotor. The period determination module determines a first length of time between a first set of induced
8271863 Forward decision aided nonlinear Viterbi detector September 18, 2012
A system, apparatus, and method are provided for a nonlinear Viterbi detector that may be used in an iterative decoding system or any other system with multiple, interconnected detectors. At least one of the Viterbi detectors may estimate the digital information sequence in a receive
8270909 Sounding and steering protocols for wireless communications September 18, 2012
The present disclosure includes systems, apparatuses, and techniques relating to wireless local area network devices. Systems, apparatuses, and techniques include communicating with multiple wireless communication devices to determine characteristics of spatial wireless channels, det
8270194 Distributed flash memory storage manager systems September 18, 2012
A flash memory storage system may include several modules of flash memory storage manager circuitry, each having some associated flash memory. The modules may be interconnected via the flash memory storage manager circuitry of the modules. The system may be able to write data to and/or
8269886 Methods and systems for improving low-resolution video September 18, 2012
Systems and methods are provided for improving the visual quality of low-resolution video displayed on large-screen displays. A video format converter may be used to process a low-resolution video signal from a media providing device before the video is displayed. The video format co
8269440 Motor speed control system and method without pulse-width modulation September 18, 2012
A motor control system includes a power control module and a detection module. The power control module controls power applied to first and second stator coils of a motor to rotate a rotor. The rotor induces voltages in the first and second stator coils when the rotor is rotating. Th
8266495 Systems and methods for performing concatenated error correction September 11, 2012
A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data
8265215 Method and system for determining symbol boundary timing in a multicarrier data transmission sys September 11, 2012
Improved techniques for acquiring symbol boundary timing at a receiver of a multicarrier data transmission system during a training sequence are disclosed. One aspect is symbol boundary determination at a receiver wherein minimal interference is used as a criterion in selecting from a
8264610 Shared memory multi video channel display apparatus and methods September 11, 2012
The invention includes a system and the associated method for decoding multiple video signals. The video signals may be component video, composite video or s-video signals each having multiple portions using a multimode video decoder. A selection stage may combine the multiple video
8259851 Method and apparatus of cross-correlation September 4, 2012
Briefly, a method and apparatus to calculate cross-correlation values of complex binary sequences are provided. The apparatus may include a transformation unit and a cross-correlator. The cross-correlator may include a cross-correlation controller to provide, based on a type bit and
8259835 Variable codebook for MIMO system September 4, 2012
A MIMO wireless communication system employing a variable size preceding codebook is provided. The size of the codebook may be determined by the quality of the wireless transmission channel between a transmitter and a receiver associated with the MIMO wireless communication systems or so
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