| Patent Number |
Title Of Patent |
Date Issued |
| RE40971 |
Direct drive programmable high speed power digital-to-analog converter |
November 17, 2009 |
| A current source is provided according to the present invention. The current source includes N current sources configured in a parallel arrangement, wherein N is at least two. Each of the N current sources includes a respective control input. The current source also includes M delay |
| RE39026 |
Bus protocol |
March 21, 2006 |
| A write-only data transfer protocol for peripheral component interface busses and a method for transferring data between source and destination communication units is provided. The method includes the source communication unit writing a buffer allocation request to the destination un |
| RE38455 |
Controllable integrator |
March 9, 2004 |
| Integrated circuitry for selectively introducing capacitance and for controlling the transconductance transfer function of one or more amplifiers includes concatenated differential amplifiers with one or more pairs of switchable capacitive components differentially connected across o |
| RE37751 |
Apparatus and method for transient suppression in synchronous data detection systems |
June 18, 2002 |
| Disclosed is a method for transient suppression in synchronous data protection systems which includes high-pass filtering of the signal produced by the sampling and shaping circuits before the signal enters the timing and gain control circuits. This high-pass filtering may be turned |
| RE37716 |
High-speed, low power, medium resolution analog-to-digital converter and method of stabilization |
May 28, 2002 |
| A full flash analog to digital converter operates on an input voltage with a track/hold circuit coupled to a reference input of each of multiple comparators. Particular track/hold circuits are activated in sequence through a track/hold select circuit, and a look-up table and a digita |
| RE37335 |
Ripple carry logic and method |
August 21, 2001 |
| Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input regist |
| 7624388 |
Caching run-time variables in optimized code |
November 24, 2009 |
| In one embodiment, the present invention includes a method for emitting a live range statement into a program for a memory variable to be cached during run-time that has at least one simulation state variable if the memory variable is dynamically mapped, and defining the simulation state |
| 7624197 |
Apparatus and method for automatic speed downshift for a two pair cable |
November 24, 2009 |
| A physical layer of a first network device is connected to cable of an Ethernet network. A digital signal processor (DSP) is connected to the cable. The DSP receives and decodes first signals on the cable from a second device. The DSP codes and transmits second signals to the second |
| 7623721 |
High-speed dithering architecture |
November 24, 2009 |
| A filter for implementing Floyd Steinberg two-dimensional error diffusion algorithms allows high-speed processing of video and images. The filter is shown in direct form with proper bit precision with implementations that permit the filter to operate at high speed. Furthermore, a reducti |
| 7623595 |
Digital technique of compensating mismatches between in phase and quadrature channels |
November 24, 2009 |
| Methods and systems for filtering an input signal include receiving a first demodulated signal produced by multiplying a first generated signal with a received input signal, receiving a second demodulated signal produced by multiplying a second generated signal with the received input |
| 7623441 |
Scalable space-frequency coding for MIMO systems |
November 24, 2009 |
| A transceiver in an N.times.N MIMO (Multiple-In-Multiple-Out) system includes a mode selection module to select a spatial multiplexing rate and a coding module to space frequency code OFDM (Orthogonal Frequency Division Multiplexing) symbols in response to the selected spatial multip |
| 7623316 |
Circuit and method for protecting emergency head-retract capacitor in a hard disk drive |
November 24, 2009 |
| A charging system includes a current source, a voltage pump, and a comparator that compares a charging level of a capacitor to each of a first threshold and a second threshold. A controller turns on the voltage pump and turns off the current source after the charging level exceeds th |
| 7623315 |
Circuits, systems, and methods for capacitive fly height measurement |
November 24, 2009 |
| Circuitry, systems, and methods for measuring the fly height of a read/write head in a magnetic data storage system. The circuitry generally includes a measurement circuit configured to determine an electrical current of a periodic signal applied to the read/write head, wherein the p |
| 7623060 |
Systems and methods for detecting radar |
November 24, 2009 |
| A system includes a first-in first-out (FIFO) module, a polling module, a data extraction module, and a control module. The FIFO module receives records having dynamic frequency selection (DFS) information generated based on pulses received and generates a control signal for every N of |
| 7623052 |
Strong short-pulse interference detection method |
November 24, 2009 |
| A system for detecting interference includes an automatic gain control (AGC) module, a peak detection module, and a control module. The AGC module selectively generates a gain-locked signal when an input signal is received. The peak detector module communicates with the AGC module and |
| 7623048 |
DC-free codes |
November 24, 2009 |
| An encoder comprises a DC tracking device that generates a metric based on portions of a communication signal and an invert signal as a function of the metric, wherein the invert signal has a flip state and a nonflip state. An inverter that selectively inverts the portions based on said |
| 7622880 |
Voice-coil motor control with zero-current sensing |
November 24, 2009 |
| A circuit for controlling a voice-coil motor (VCM) may incorporate a pulse-width modulation driver to drive the VCM, a zero-current detector to determine whether the current across the VCM is zero, and a Back-EMF voltage detector to measure the voltage across the VCM when the current |
| 7619975 |
Generalized auto media selector |
November 17, 2009 |
| A network media selection system comprises a memory that stores priority information for each of a plurality of ports and a media selector module that communicates with the memory, that receives activity signals and link signals from the plurality of ports, and that uses the activity |
| 7616719 |
Compensation for residual frequency offset, phase noise and sampling phase offset in wireless ne |
November 10, 2009 |
| Improved performance, particularly gain in signal-to-noise ratio (SNR), in high-bandwidth Orthogonal Frequency Division Multiplexing (OFDM) receivers, software and systems is achieved by compensating channel estimates not only for carrier frequency offset and phase noise, but also fo |
| 7616695 |
MIMO equalizer design: an algorithmic perspective |
November 10, 2009 |
| A receiver in a MIMO-OFDM system may estimate the transmitted signal by performing a QR decomposition on the channel response matrix. The receiver may utilize Givens rotations to perform the decomposition, which may be performed using coordinate rotation digital computer (CORDIC) mod |
| 7616587 |
Methods and apparatus for performing reverse auto-negotiation in network communication |
November 10, 2009 |
| The present invention relates to methods and apparatus for performing reverse auto-negotiation, in which one network device establishes a link with another network device at a preferred operating mode (e.g., the lowest speed) common to both devices without linking twice. The physical |
| 7613967 |
Inversion of scan clock for scan cells |
November 3, 2009 |
| A device includes a scan circuit including a scan chain. The scan chain includes a first plurality of scan cells that receive a first scan clock signal in a first clock domain. A second plurality of scan cells receives a second scan clock signal in a second clock domain. A scan clock sou |
| 7613887 |
System and method for managing a memory storage device |
November 3, 2009 |
| A memory management system for a memory in a data storage device comprises a memory controller module that receives a frame of data including a plurality of data words from a host, that generates boundary indicators based on at least one of a start and an end of the frame and the plu |
| 7613838 |
Low overhead coding with arbitrary control code placement |
November 3, 2009 |
| A physical layer device of a network device comprises a physical coding sublayer (PCS) device encodes data to produce an encoded data block. A scrambler communicates with the PCS device and scrambles the encoded data block to produce a scrambled data block. A sync adder adds a sync heade |
| 7613249 |
Spurious component reduction |
November 3, 2009 |
| Apparatus, systems, and methods implementing techniques for reducing spurious components are described. According to one aspect, a wideband polyphase filter filters an input signal that has an associated first frequency. The wideband polyphase filter has poles corresponding to a firs |
| 7612697 |
Rate-28/30 DC-free RLL code |
November 3, 2009 |
| A run-length limited (RLL) encoder includes a block detection module that receives a data block that includes N portions and generates N-1 coding bits indicating whether corresponding ones of N-1 of the N portions of the data block include one of all ones and all zeros, where N is an |
| 7610164 |
System and method of constant power biasing circuit |
October 27, 2009 |
| A system is provided to adjust a separation distance between a read/write sensing head and a data storage medium surface in a hard disk. The thermal expansion of the sensing head based on heat generated by power dissipated through the sensing head is precisely controlled. When electr |
| 7610022 |
Filter circuit with negative transconductance |
October 27, 2009 |
| Apparatus, systems, and methods implementing techniques for filtering signals are described. A filter circuit receives an input signal and produces a corresponding filtered signal. The filter circuit has a transfer function that relates the filtered signal to the input signal. The tr |
| 7609538 |
Logic process DRAM |
October 27, 2009 |
| A semiconductor integrated circuit device includes a dynamic random access memory (DRAM) unit. The DRAM unit comprises a plurality of bit line pairs. Each bit line pair includes a first bit line and a second bit line. The first bit line and the second bit line within each bit line pa |
| 7609468 |
Method and system for read gate timing control for storage controllers |
October 27, 2009 |
| A disk controller that controls data transfer between a storage device and a host system is provided. The disk controller includes logic having a state machine that controls de-assertion of a read gate signal based on sector size and/or whether a data segment is split or non-split. The r |
| 7609186 |
Circuit for converting a voltage range of a logic signal |
October 27, 2009 |
| In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second transistor selectively discharges |
| 7607073 |
Methods, algorithms, software, circuits, receivers and systems for iteratively decoding a tailbi |
October 20, 2009 |
| Methods, software, circuits and systems involving a low complexity, tailbiting decoder. The method relates to appending and/or prepending data subblocks to a serial data block, decoding and estimating starting and ending states for the serial data block, and when the starting and end |
| 7606547 |
Active resistance summer for a transformer hybrid |
October 20, 2009 |
| An electrical circuit in a communications channel includes a first sub-circuit having a first input which receives a composite signal that includes a transmission signal component and a receive signal component, a second input which receives a replica transmission signal, a third inp |
| 7606316 |
MIMO-OFDM preamble for channel estimation |
October 20, 2009 |
| A preamble for a MIMO-OFDM system includes multiple training symbols. Each training symbol has a pattern in which data symbols and null symbols are transmitted on all tones and on all transmit antennas. The pattern for each training symbol corresponds to a cyclic shift of the patterns of |
| 7606296 |
Decoding method and apparatus |
October 20, 2009 |
| A decoder comprises an equalizer that receives a modulated signal comprising a plurality of symbols including a first symbol defined by a first number of chips. A subsymbol processor that generates a subsymbol waveform after receiving a second number of chips of the first symbol and |
| 7606230 |
Link aggregation for routed ports |
October 20, 2009 |
| A wireless network apparatus and corresponding method and computer program comprises a plurality of ports to transmit and receive data flows comprising packets of data; a memory to store a routing table; a forwarding engine to transfer the packets of data between the ports according |
| 7606016 |
Power amplifier protection |
October 20, 2009 |
| A power amplifier protection circuit that includes protection circuitry to variably shunt an input radio frequency (RF) signal to AC ground, turn off bias to an output transistor of a power amplifier, and turn off the output transistor. The power amplifier protection circuit features an |
| 7605608 |
Circuit for converting a voltage range of a logic signal |
October 20, 2009 |
| In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A secon |
| 7602864 |
Method and apparatus for predicting CCK subsymbols |
October 13, 2009 |
| A correlator comprises a plurality of phase rotators, a plurality of combining modules, a plurality of computation modules, and a selection module. The plurality of phase rotators selectively modifies phase for each chip of a first subset of chips by one of M phase offsets, where an |
| 7602568 |
Synchronous RRO write |
October 13, 2009 |
| A hard disk drive system includes a control module that generates a phase offset signal for a repeatable run out (RRO) field of a servo wedge based on an RRO phase of the RRO field and a data phase of data in at least one other servo wedge field of a previously written wedge. A read/writ |
| 7602131 |
Voice coil motor control system and method using pulse width modulation |
October 13, 2009 |
| A system includes a current control module that supplies current to a voice coil motor during a first period to rotate an actuator arm in a first rotational direction, that discharges the current from the voice coil motor after the first period, and that generates a control signal a |
| 7600084 |
Register file with integrated routing to execution units for multi-threaded processors |
October 6, 2009 |
| A multi-context register file for use in a multi-threaded processor includes at least one multi-context register file cell having internal routing functionality. |
| 7599663 |
Apparatus and method for measuring signal quality of a wireless communications link |
October 6, 2009 |
| An apparatus comprises a link interface to receive an OFDM symbol from a communications link. A signal-to-noise ratio estimation unit generates an estimate of a geometric signal-to-noise ratio for the received symbol based on a function of the soft and hard decisions. A signal quality of |
| 7599456 |
Input/output data rate synchronization using first in first out data buffers |
October 6, 2009 |
| An input/output data rate synchronization system includes a first data buffer that receives input data at a first rate, that temporarily stores the input data, and that outputs the input data at a second rate. A data processing module receives the input data from the first data buffer an |
| 7599424 |
Antenna diversity technique for wireless communication |
October 6, 2009 |
| A receiver includes a demodulator that receives data packets each having a preamble and that generates spreading codewords by correlating a spreading code with the preambles of the data packets. A signal quality device determines signal quality values at a plurality of antennas for e |
| 7599391 |
Media and speed independent interface |
October 6, 2009 |
| A rate adaptation layer (RAL) module for converting from a first interface operating at a first rate to a second interface operating at a second rate comprises first and second input/output (I/O) modules that communicate with the first and second interfaces, respectively. A repeater |
| 7598814 |
Method and apparatus for an LNA with high linearity and improved gain control |
October 6, 2009 |
| A low noise amplifier (LNA) circuit includes a linear input stage including a first circuit that generates an output current and has a low input impedance. A device receives an input signal, communicates with the low impedance input of the first circuit, and includes a variable resis |
| 7596731 |
Test time reduction algorithm |
September 29, 2009 |
| Exemplary embodiments provide a method and system for reducing test time for electronic devices. The method and system aspects include receiving a test data file containing results from a set of tests run on a first set of devices; determining a frequency of failure metric for each of th |
| 7596182 |
Optimum symbol timing estimation with various performance measures for OFDM systems |
September 29, 2009 |
| A receiver in an OFDM system may include a multi-mode estimator to estimate symbol timing offset for different performance measures. In addition to a maximum likelihood estimation mode, the estimator may have a minimum failure probability estimation mode, a minimum mean square error |
| 7596053 |
Integrated memory controller |
September 29, 2009 |
| A circuit for reading data from a buffer memory, which is Synchronous Dynamic Random access Memory ("SDRAM"), or Double Data Rate-Synchronous Dynamic Random Access Memory ("DDR") comprises logic for managing programmable clock signal relationships such that data that is read from the |
