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Macronix International Co., Ltd. Patents
Assignee:
Macronix International Co., Ltd.
Address:
Hsinchu, TW
No. of patents:
1605
Patents:












Patent Number Title Of Patent Date Issued
D548643 Award trophy August 14, 2007
8589716 Clock integrated circuit November 19, 2013
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.
8587998 3D memory array with read bit line shielding November 19, 2013
A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string
8587983 Resistance random access memory structure for enhanced retention November 19, 2013
A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the
8586960 Integrated circuit including vertical diode November 19, 2013
An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element
8586442 Manufacturing method for high voltage transistor November 19, 2013
A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are fo
8581339 Structure of NPN-BJT for improving punch through between collector and emitter November 12, 2013
A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collect
8581327 Memory and manufacturing method thereof November 12, 2013
A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and th
8581322 Nonvolatile memory device and method for making the same November 12, 2013
A method for making a nonvolatile memory device includes the following steps. A conductive structure is formed, wherein the conductive structure has a first top portion. The first top portion is converted into a second top portion having a domed surface.
8574992 Contact architecture for 3D memory array November 5, 2013
A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding cir
8570806 Z-direction decoding for three dimensional memory array October 29, 2013
The switch transistors in the NAND strings have combinations of threshold voltage levels that vary across the levels of a three dimensional memory array. A bias arrangement is applied to the select lines electrically coupled to the switch transistors. The NAND strings on a particular lev
8569822 Memory structure October 29, 2013
A memory structure having a memory cell including a first dielectric layer, a gate, a semiconductor layer, a first doped region, a second doped region and a charge storage layer is provided. The first dielectric layer is on the substrate. The gate includes a base portion on the first
8566755 Method of correcting photomask patterns October 22, 2013
A method of predicting photoresist patterns defined by a plurality of photomask patterns is described. The measurement data of photoresist patterns defined by patterns on a photomask that are arranged similar to the photomask patterns are provided. A physical optical kernel and a mat
8564099 Semiconductor structure and a method for manufacturing the same October 22, 2013
A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first cond
8300476 Method for erasing/programming/correcting memory October 30, 2012
A memory operating method includes the following steps. First, a memory with a charge storage structure is provided. Next, the memory is biased to a first threshold voltage. Then, the memory is biased to a second threshold voltage. Next, the memory is biased to a third threshold volt
8298952 Isolation structure and formation method thereof October 30, 2012
An isolation structure comprising a substrate is provided. A trench is in the substrate. A sidewall of the trench has a first inclined surface and a second inclined surface. The first inclined surface is located on the second inclined surface. The slope of the first inclined surface is
8295094 Method of operating non-volatile memory cell October 23, 2012
A method of operating a memory cell for 3D array of this invention is described as follows. Carriers of a first type are injected into a charge storage layer of the memory cell by applying a double-side biased (DSB) voltage to double sides of the memory cell. Carriers of a second type ar
8295086 Memory array October 23, 2012
A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit line
8295075 Resistive memory and method for controlling operations of the same October 23, 2012
A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer
8294278 Methods for pitch reduction October 23, 2012
An integrated circuit described herein includes a substrate and a plurality of lines overlying the substrate. The lines define a plurality of first trenches and a plurality of second trenches. The plurality of first trenches extend into the substrate a distance different than that of
8293600 Thermally stabilized electrode structure October 23, 2012
Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode layer, and a thermal isolation structure including a layer of thermal isolation material between the first and second electrode
8288815 Gate structure of semiconductor device having a conductive structure with a middle portion and t October 16, 2012
A gate structure for a semiconductor device is provided. The gate structure includes a conductive structure. The conductive structure insulatively disposed over a substrate includes a middle portion and two spacer portions. The middle portion has a first surface and two second surfac
8288280 Conductor removal process October 16, 2012
A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP
8284597 Diode memory October 9, 2012
A diode memory device has an intermediate structure between the two terminals, such as a p terminal and the n terminal.
8281411 Security memory device and method for making same October 2, 2012
A security memory device includes a memory cell array that stores a plurality of contents, including a mine, which is stored as a portion of the plurality of contents. The mine is triggered when it is accessed, typically such that the mine erases the memory contents. Also, control lo
8279656 Nonvolatile stacked nand memory October 2, 2012
A memory cell is arranged to enhance the electrical field of the memory element. The memory cell has a metal-oxide memory element, a nonconductive element, and a conductive element. The metal-oxide memory element is in a current path between a first electrode at a first voltage and a
8278770 Overlay mark October 2, 2012
The invention is directed to an overlay mark in a first material layer in an overlay alignment region of a wafer and the first material layer is made from a first material. The overlay mark includes a plurality of mark regions and each of the mark regions comprises a plurality mark eleme
8275929 Memory and operating method thereof September 25, 2012
A method of programming data stored in a memory, which comprises a number of user-defined blocks, a number of manufacture-defined blocks, and an information block, includes the following steps. A programming address pointing to a user-defined block in the memory and programming data is
8275353 System and method of managing contactless payment transactions using a mobile communication devi September 25, 2012
A method handling payment transactions in a system using mobile communication devices as stored value devices is disclosed. A transaction operations server receives multiple records of the transaction from the stored value device--one via a communication channel through the telecommu
8274065 Memory and method of fabricating the same September 25, 2012
A memory, comprising a metal portion, a first metal layer and second metal oxide layer is provided. The first metal oxide layer is on the metal portion, and the first metal oxide layer includes N resistance levels. The second metal oxide layer is on the first metal oxide layer, and t
8273598 Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process September 25, 2012
A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material
8270245 Memory Device September 18, 2012
A memory device comprises first memory block having first boundary cell and second memory block having second boundary cell. Data of the first and the second boundary cells are outputted simultaneously corresponding to a plurality of column selection signals.
8270223 Memory device September 18, 2012
A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate t
8264900 Data sensing arrangement using first and second bit lines September 11, 2012
Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and
8264878 Method and apparatus for increasing memory programming efficiency through dynamic switching of b September 11, 2012
A method of efficiently programming charge-trapping memory cells includes sense amplifiers being dynamically connected to cells to be programmed, by switching bit lines. The method increases a number of cells that can be programmed simultaneously, such that an optimal use of sense amplif
8264028 Non-volatile memory cells, memory arrays including the same and methods of operating cells and a September 11, 2012
Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at lea
8263960 Phase change memory cell with filled sidewall memory element and method for fabricating the same September 11, 2012
Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode, a top electrode overlying the bottom electrode, a via having a sidewall extending from a bottom electrode to a top electrode, and a memory element electrically
8261120 Clock integrated circuit September 4, 2012
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.
8259521 Method and circuit for testing a multi-chip package September 4, 2012
A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the
8259499 Method and apparatus of performing an erase operation on a memory integrated circuit September 4, 2012
Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected
8259492 Method of reading dual-bit memory cell September 4, 2012
A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling
8259484 3D chip selection for shared input packages September 4, 2012
A multi-chip package with die having shared input and unique access IDs. A unique first ID is assigned and stored on die in a die lot. A set of die is mounted in a multi-chip package. Free access IDs are assigned by applying a sequence of scan IDs on the shared input. On each die, the
8258815 Clock generator circuits for generating clock signals September 4, 2012
The present invention relates to a circuit for generating a clock signal. The circuit comprises a current source to generate a reference current and provide a first voltage V.sub.1, a first current generator to generate a first mirror current during a first half cycle based on the re
8258042 Buried layer of an integrated circuit September 4, 2012
Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type bu
8258029 Semiconductor structure and process for reducing the second bit effect of a memory device September 4, 2012
A non-volatile memory cell capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in association with at least one electrical dielectric layer, such as an oxide, with a P-type substrate and an N-type channel imp
8253165 Structures for lowering trigger voltage in an electrostatic discharge protection device August 28, 2012
A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within
8252654 Method for manufacturing memory cell August 28, 2012
In a method for manufacturing a memory cell, a substrate is provided. A doped region with a first conductive type is formed in the substrate near a surface of the substrate. A portion of the substrate is removed to define a plurality of fin structures in the substrate. A plurality of
8245074 Clock integrated circuit August 14, 2012
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.
8243494 Self-aligned structure and method for confining a melting point in a resistor random access memo August 14, 2012
A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body,
8243489 Memory device no common source region and method of fabricating the same August 14, 2012
A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word

 
 
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