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Lattice Semiconductor Corporation Patents
Assignee:
Lattice Semiconductor Corporation
Address:
Hillsboro, OR
No. of patents:
454
Patents:


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Patent Number Title Of Patent Date Issued
RE40311 Zero-power programmable memory cell May 13, 2008
A zero-power electrically erasable and programmable memory cell is implemented in CMOS (complementary metal oxide semiconductor) technology. A P-channel sense transistor has a source coupled to a first voltage generator, and an N-channel sense transistor has a source coupled to a sec
RE39510 FPGA integrated circuit having embedded sram memory blocks with registered address and data inpu March 13, 2007
A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has a re
8286116 Composite wire indexing for programmable logic devices October 9, 2012
Various techniques are disclosed to identify composite wires from segmented wires of a programmable logic device (PLD). In one example, a method includes associating segmented wires of the PLD with a plurality of wire index values based on connections identified by interface template
8274412 Serializer with odd gearing ratio September 25, 2012
In certain embodiments of the invention, a serializer has (a) an initial, transfer stage that transfers incoming parallel data from a relatively slow timing domain to a relatively fast timing domain and (b) a final, serializing stage that converts the parallel data into serialized data.
8261160 Synchronization of serial data signals September 4, 2012
Various techniques are provided for synchronizing serial data signals received by electronic systems or devices such as programmable logic devices (PLDs). In one example, a method of synchronizing data includes receiving a serial data signal at a device. The serial data signal operat
8255733 Clock delay and skew control systems and methods August 28, 2012
A method of providing a clock signal for an embodiment includes performing a calibration for a closed loop control system to determine a control signal value that provides a desired tuning of the closed loop control system. The control signal value is stored and provided to a delay c
8248136 Low-power, glitch-less, configurable delay element August 21, 2012
In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8.times.1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first
8200179 Combined variable gain amplifier and analog equalizer circuit June 12, 2012
In one embodiment, a combined VGA-and-equalizer (VGA-EQ) circuit for a communication link includes a current-mode logic ("CML") amplifier with an inductive load circuit. The CML amplifier has a gain control terminal and is operable to amplify, with an adjustable gain, a signal received a
8169237 Comparator with jitter mitigation May 1, 2012
In one embodiment, a circuit such as a comparator circuit includes a differential stage adapted to receive a differential input signal and first and second diodes coupled to the differential stage. The first and second diodes are adapted to selectively switch on and off to provide a
8165164 In-system reconfigurable circuit for mapping data words of different lengths April 24, 2012
A mapping circuit is provided for mapping first data words into frames of second data words, wherein the first and second data words are of different length. In addition, a de-mapping circuit is provided for de-mapping the frames of second data words into the first data words. The ma
8164499 Shared-array multiple-output digital-to-analog converter April 24, 2012
In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial coefficient COEFF
8138790 Latency measurements for wireless communications March 20, 2012
In one embodiment, a programmable logic device (PLD) includes a programmable fabric and hard logic coupled to the programmable fabric. The hard logic includes a timing measurement circuit adapted to measure latency of a data path between first and second points in the programmable lo
8132040 Channel-to-channel deskew systems and methods March 6, 2012
Systems and methods are disclosed herein to provide channel-to-channel skew control in accordance with one or more embodiments of the present invention. For example in accordance with an embodiment, a method of adjusting skew between first and second channels includes receiving a fir
8122277 Clock distribution chip February 21, 2012
In one embodiment, a clock distribution chip includes a clock input adapted to receive an input clock signal, clock dividers each adapted to receive a clock signal based on the first input clock signal and to generate a divided clock signal, and programmable clock outputs adapted to
8112731 Congestion-driven placement systems and methods for programmable logic devices February 7, 2012
Techniques are provided for reducing signal congestion in programmable logic devices (PLDs). In one example, a computer-implemented method of reducing signal congestion in a configuration of a PLD includes mapping a plurality of circuit components of a circuit design to a plurality of
8112656 Clock distribution chip February 7, 2012
In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended input clock signal, and input buffer circuitry coupled to the first and second clock inputs.
8108754 Programmable logic device programming verification systems and methods January 31, 2012
In one embodiment, a method of verifying a programming operation of a programmable logic device includes storing in non-volatile memory within the programmable logic device configuration data and a pre-calculated code value based on the configuration data. The method further includes
8104009 Wire mapping for programmable logic devices January 24, 2012
A computer-implemented method of referencing wires of a routing graph of a programmable logic device (PLD). In one embodiment, the method includes mapping the first routing graph wire to a master wire; mapping the first master wire to master switch; identifying a segmented wire connected
8086986 Clock boosting systems and methods December 27, 2011
In one embodiment of the invention, a programmable logic device (PLD) includes logic blocks, registers corresponding to the logic blocks, and configuration memory adapted to store configuration data for configuring the PLD. Also included in the PLD is a general routing network having a
8069431 Routing signals to pins of components in programmable logic devices November 29, 2011
Various techniques are provided for routing signals to pins of components of programmable logic devices (PLDs). In one example, a computer-implemented method of routing signals in a PLD includes routing a plurality of signals to pins of a component of the PLD. At least two of the sig
8069329 Internally triggered reconfiguration of programmable logic devices November 29, 2011
Various techniques are described to provide an internally triggered reconfiguration of a programmable logic device (PLD). In one example, a PLD includes configuration memory adapted to store first configuration data to configure the PLD for its intended function. The PLD also include
8065574 Soft error detection logic testing systems and methods November 22, 2011
A programmable logic device, in accordance with one embodiment, includes a plurality of configuration memory cells, wherein at least one configuration memory cell is adapted to function as random access memory. Read/write circuitry writes to and reads from a corresponding first port
8060784 Programmable logic device and methods for providing multi-boot configuration data support November 15, 2011
In one embodiment of the invention, a programmable logic device includes configuration memory and a controller. The controller can read a first bitstream from a first memory block of non-volatile memory and detect whether the first bitstream contains a valid preamble as the first bit
8059470 Flash memory array with independently erasable sectors November 15, 2011
In one embodiment, an integrated circuit includes a flash memory array with at least first and second subarrays, or sectors, of memory cells. The subarrays have a set of shared bitlines and separate sets of word lines. A bitline driver circuit is coupled to the set of shared bitlines,
8058898 Compression and decompression of configuration data using repeated data frames November 15, 2011
In one embodiment, a method of converting an uncompressed bitstream into a compressed bitstream for a programmable logic device (PLD) is disclosed. The method includes embedding a first data frame from the uncompressed bitstream into the compressed bitstream, wherein the first data f
8040159 Comparator with jitter mitigation October 18, 2011
In one example, a comparator circuit includes a differential stage adapted to receive a differential input signal. The comparator circuit includes first and second diodes coupled to the differential stage. The first and second diodes are adapted to selectively switch on and off to pr
8040152 Separate configuration of I/O cells and logic core in a programmable logic device October 18, 2011
A programmable logic device (PLD) is provided that includes: a plurality of programmable logic blocks, the plurality of programmable logic blocks being associated with a first configuration data shift register operable to shift in configuration data for the plurality of programmable logi
8010871 Auto recovery from volatile soft error upsets (SEUs) August 30, 2011
A method of recovering from a soft error within configuration data stored in a configured programmable logic device. The method includes repeatedly processing the configuration data stored within configuration memory of the device using an error-detection algorithm to generate a checksum
7992120 Congestion estimation for programmable logic devices August 2, 2011
Various techniques are provided for estimating signal congestion in a programmable logic device (PLD). In one example, a computer-implemented method of estimating signal congestion in routing resources of a PLD is provided. The routing resources comprise a plurality of nodes and a pl
7989911 Shallow trench isolation (STI) with trench liner of increased thickness August 2, 2011
In one embodiment, an integrated circuit includes a substrate having high voltage transistor regions and low voltage transistor regions. The substrate includes a first trench between and adjacent to the high voltage transistor regions, a second trench between and adjacent to the low
7985656 Shallow trench isolation (STI) with trench liner of increased thickness July 26, 2011
A method of manufacturing an integrated circuit includes etching a substrate to create simultaneously a first trench between high voltage transistor regions of the substrate and a second trench between low voltage regions of the substrate. The substrate is then oxidized to form a sil
7969248 Oscillator tuning for phase-locked loop circuit June 28, 2011
In one example, a method of tuning an oscillator of a phase-locked loop (PLL) circuit includes adjusting a coarse control signal to select one of a plurality of frequency tuning curves of the oscillator. The method includes adjusting a fine control signal to select a position on the
7957208 Flexible memory architectures for programmable logic devices June 7, 2011
In one embodiment, a programmable logic device includes a plurality of logic blocks; a plurality of input/output blocks; volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks; embedded block RAM adapted to store us
7944765 Programmable logic device with built in self test May 17, 2011
In one embodiment of the invention, an integrated circuit such as a programmable logic device includes volatile memory, nonvolatile memory, and a data shift register for reading data from the nonvolatile memory and for reading data from and writing data to the volatile memory. A buil
7924054 Latency measurements for wireless communications April 12, 2011
A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES channels and transmits
7902865 Compression and decompression of configuration data using repeated data frames March 8, 2011
Various techniques are provided to compress and decompress configuration data for use with programmable logic devices (PLDs). In one example, a method includes embedding a first data frame comprising a data set from an uncompressed bitstream into a compressed bitstream. The method also
7897448 Formation of high voltage transistor with high breakdown voltage March 1, 2011
A high voltage transistor exhibiting an improved breakdown voltage and related methods are provided. For example, a method of manufacturing an integrated circuit includes etching a poly silicon layer to provide a gate stacked above a floating gate of a flash memory cell. A source and a
7895555 Simultaneous switching output noise estimation and reduction systems and methods February 22, 2011
Systems and methods provide improved techniques directed to simultaneous switching output (SSO) noise, which for example may be applied during the programmable logic device design process. For example in accordance with an embodiment, a method of structuring simultaneous switching output
7890913 Wire mapping for programmable logic devices February 15, 2011
Various techniques for referencing components of a programmable logic device (PLD) are provided. In one example, a method of referencing wires of a routing graph of a PLD is provided. The routing graph comprises a plurality of routing graph wires and a plurality of routing graph swit
7876125 Register data retention systems and methods during reprogramming of programmable logic devices January 25, 2011
Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in one embodiment, a programmable logic device includes a plurality of logic blocks adapted to generate use
7868654 Reading an external memory device to determine its interface characteristics for configuring a p January 11, 2011
Various techniques are provided for determining interface characteristics of external devices. In one example, a method of configuring a programmable logic device (PLD) with configuration data stored in one or more external memory devices includes reading by the PLD an interface setu
7868646 Soft error upset hardened integrated circuit systems and methods January 11, 2011
In one embodiment, a programmable logic device includes a plurality of configuration cells that store configuration data, wherein the programmable logic device is adapted to provide soft error upset (SEU) protection for the configuration cells that are reprogrammable. The programmabl
7863931 Flexible delay cell architecture January 4, 2011
A flexible delay cell architecture and related methods are provided that may be used, for example, with input/output (I/O) blocks of a programmable logic device (PLD). In one implementation, a PLD includes a delay cell comprising a plurality of delay elements. The delay elements are
7844243 Receiver for differential and reference voltage signaling with programmable common mode November 30, 2010
In one embodiment of the invention, a receiver has two mux circuits, two receiver circuits, and a mixer. The muxes select first and second input signals for the receiver circuits. A p-type transistor in a transmission gate in each mux is connected (i) at its channel nodes between a pad a
7834652 Method and devices for storing a security key using programmable fuses November 16, 2010
In embodiment of the invention, a programmable logic device includes configuration memory adapted to be programmed with configuration data and a plurality of programmable fuses adapted to store a security key for use with configuration data. The security key includes a plurality of data
7831856 Detection of timing errors in programmable logic devices November 9, 2010
In one example, a method of detecting timing errors in a configuration of a programmable logic device (PLD) includes performing a timing analysis on the PLD configuration. The PLD configuration is adapted to configure the PLD to perform a data transfer between a first clock domain sy
7831754 Multiple communication channel configuration systems and methods November 9, 2010
An integrated circuit includes, in accordance with an embodiment of the present invention, a data port, a system bus for transferring information to and from the data port, and a plurality of SERDES channels. A plurality of registers associated with the plurality of SERDES channels m
7808855 Distributed front-end FIFO for source-synchronous interfaces with non-continuous clocks October 5, 2010
In one embodiment, an integrated circuit such as an FPGA includes one or more data I/O blocks, one or more FIFOs, and a FIFO controller. At least one data I/O block receives an incoming bit stream from an external device. At least one FIFO is connected to receive a corresponding inco
7808405 Efficient bitstream compression October 5, 2010
In one embodiment of the invention, a method of generating a compressed configuration bitstream for a programmable logic device comprises encoding the most-prevalent data word within the configuration data of the bitstream into a codeword of a first type; encoding a set of more-preva
7788623 Composite wire indexing for programmable logic devices August 31, 2010
Various techniques are described to identify composite wires from segmented wires of a programmable logic device (PLD). In one example, a method includes identifying a plurality of interface templates corresponding to tiles of the PLD. The PLD comprises a plurality of segmented wires
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