| Patent Number |
Title Of Patent |
Date Issued |
| 7061822 |
Clock generator for pseudo dual port memory |
June 13, 2006 |
| A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a r |
| 7061410 |
Method and/or apparatus for transcoding between H.264 CABAC and CAVLC entropy coding modes |
June 13, 2006 |
| An apparatus comprising a first circuit, a second circuit and an output circuit. The first circuit may be configured to generate (i) one of a first set of entropy coded input signals or a second set of entropy coded input signals and (ii) a data path signal. The second circuit may be |
| 7061267 |
Page boundary detector |
June 13, 2006 |
| A logical gate and a comparator are used to detect page boundaries in a data stream. A current address and a predetermined page size, that is an integer power of 2, are compared using a Boolean logic gate such as AND or XOR to detect a page boundary in a data stream. The output from the |
| 7058909 |
Method of generating an efficient stuck-at fault and transition delay fault truncated scan test |
June 6, 2006 |
| A method of generating a truncated scan test pattern for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) estimating a number of transition delay fault test patterns and a corresponding number of top-off stuck-at fault patterns to |
| 7058906 |
Architecture for a sea of platforms |
June 6, 2006 |
| The present invention is directed to platform architecture used for integrated circuit design. A system for providing distributed dynamic functionality in an electronic environment may include a plurality of platforms. The platforms are suitable for providing a logic function, and in |
| 7058854 |
Automode select |
June 6, 2006 |
| A microprocessor based system automatically detects the occurrence of certain conditions in the microprocessor. The conditions may include a determination of data corruption in the microprocessor. If a determination is made that data is corrupted, the microprocessor may be reloaded f |
| 7057449 |
Noise cancellation in mixed signal environment |
June 6, 2006 |
| A method of canceling noise in analog circuits is described along with noise cancellation circuits. Analog circuits are sensitive to noise. Especially in mixed signal environments where digital circuits and analog circuits are combined, the noise generated by relatively noisy digital |
| 7057261 |
Mixed LVR and HVR reticle set design for the processing of gate arrays, embedded arrays and rapi |
June 6, 2006 |
| An embodiment of the present invention provides a novel method which makes LVR to HVR registration possible by wrapping the X and Y scribes around each instance of each layer on both the LVR and HVR reticles; standard HVR reticles and LVR reticles will not align to one another due to |
| 7056392 |
Wafer chucking apparatus and method for spin processor |
June 6, 2006 |
| A wafer chuck is configured to hold a wafer efficiently for spin process cleaning of wafer edges and back sides. A first group of retractable tips extend to hold the wafer during a first portion of the cleaning period. A second group of retractable tips extend to hold the wafer during a |
| 7055113 |
Simplified process to design integrated circuits |
May 30, 2006 |
| A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control p |
| 7055068 |
Method for validating operation of a fibre link |
May 30, 2006 |
| A method for validating operation of a fiber link when the fiber link is initialized includes the steps of entering a trial link up state upon receiving a command to initialize the fiber link so that normal commands to other devices within the fiber channel loop are not resumed, and |
| 7054988 |
Bus interface for processor |
May 30, 2006 |
| The present invention may generally provide a processor circuit comprising a processor, a first bus, a bus pipeline stage, and a second bus. The first bus may be coupled to the processor. The bus pipeline stage may be coupled between the first bus and the second bus and configured to del |
| 7054972 |
Apparatus and method for dynamically enabling and disabling interrupt coalescing in data process |
May 30, 2006 |
| An apparatus and method for dynamically enabling and disabling interrupt coalescing in a data processing system. The present invention involves consistently monitoring IO load on an IOP of an IO adapter. The firmware on the IO adapter may have a global variable that stores counters for P |
| 7054606 |
Digitally calibrated narrowband filter with analog channel compensation |
May 30, 2006 |
| An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to filter an analog input signal in an analog domain in response to one or more control signals. The second circuit may be configured to convert the analog input signal |
| 7053639 |
Probing fixture for semiconductor wafer |
May 30, 2006 |
| A semiconductor wafer is placed into a probe fixture with a front side of the wafer facing up. Power and signal probes are then placed on an integrated circuit (IC) formed on the front side of the wafer. The probe fixture is retained at a test station either in a upright or an inverted |
| 7051434 |
Designing a ball assignment for a ball grid array package |
May 30, 2006 |
| A method for designing a routing pattern for electrical contacts on a printed circuit board by arranging contacts in an array of rows and columns on the printed circuit board, connecting groups of n columns of contacts to n-1 columns of vias disposed interstitially between the contac |
| 7051318 |
Web based OLA memory generator |
May 23, 2006 |
| A system for generating an Open Library Architecture Delay and Power Calculation Module. The system includes a user interface for generating and submitting requests that specify configurations and types of memories for which Open Library Architecture Delay and Power Calculation Modules |
| 7051297 |
Method and apparatus for mapping platform-based design to multiple foundry processes |
May 23, 2006 |
| The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a predefined (or pre-specified) slice is successfully mapped on to a first fabrication process with |
| 7051146 |
Data processing systems including high performance buses and interfaces, and associated communic |
May 23, 2006 |
| A processor is disclosed that executes an instruction including a user-defined value (an address or a command) and provides the user-defined value during execution of the instruction. In one embodiment the processor includes a bus interface adapted for coupling to a bus, and the proc |
| 7050582 |
Pseudo-random one-to-one circuit synthesis |
May 23, 2006 |
| A method of defining a transformation between an input signal and an output signal. The transformation may implement a pseudo-random one-to-one function that may be implemented in hardware and/or software or modeled in software. The method may comprise the steps of (A) allocating the |
| 7047470 |
Flexible and extensible implementation of sharing test pins in ASIC |
May 16, 2006 |
| A library to be used in an ASIC design system includes information to be used for verification of test structures. The library includes information regarding the ability to combine test pins for verification of the test structure and information regarding the sharing of ports for ver |
| 7047449 |
Method for providing cable isolation in a fibre channel test environment using a software driven |
May 16, 2006 |
| A cable isolator is provided for automatically performing cable breaks for testing of host bus adapters. A workstation includes a host bus adapter, such as a Fibre Channel storage controller, to be tested. The host bus adapter is connected to one or more storage modules through the cable |
| 7047335 |
Method for receiving user defined frame information structure (FIS) types in a serial-ATA (SATA) |
May 16, 2006 |
| An apparatus comprising one or more user programmable registers and a circuit configured to compare a predetermined portion of one or more information packets with contents of said one or more user programmable registers. |
| 7046033 |
Termination enable: hardware and software controlled enable with detect |
May 16, 2006 |
| A method and circuit allows flexible control for termination of a signal line. The mode of operation of the circuit may be set manually or automatically. A software controller provides software control of the signal line. A bus terminator is tied to the signal line. A feedback line f |
| 7043718 |
System real-time analysis tool |
May 9, 2006 |
| An apparatus comprising a full system monitor. The monitor may be configured to monitor in real-time one or more (i) software variables down to change rates, (ii) hardware registers down to cycle rates, and (iii) firmware registers down to microcode fetch rates. |
| 7043708 |
Intelligent crosstalk delay estimator for integrated circuit design flow |
May 9, 2006 |
| A method of estimating crosstalk delay for an integrated circuit design flow includes steps of: (a) receiving an integrated circuit design; (b) selecting a list of blocks for which crosstalk delay is to be estimated from the integrated circuit design; (c) selecting one of a plurality of |
| 7043703 |
Architecture and/or method for using input/output affinity region for flexible use of hard macro |
May 9, 2006 |
| An apparatus comprising (i) one or more input/output cells, (ii) one or more hard macros and (iii) one or more input/output affinity regions. The one or more input/output affinity regions may be disposed between the one or more input/output cells and the one or more hard macros. Each of |
| 7043670 |
Reducing the effect of simultaneous switching noise |
May 9, 2006 |
| An integrated circuit comprises a microprocessor for generating data signals along a data bus by way of an inverter to a plurality of input/output switching buffers. The buffers pass the data signals to a transmission bus for onward transmission to a receiving integrated circuit. A r |
| 7043622 |
Method and apparatus for handling storage requests |
May 9, 2006 |
| Systems and methods for handling I/O requests from a host system to a storage system. A system includes an I/O module for processing I/O requests from a host system, a virtualized storage element, and a communication medium coupling the I/O module to the virtualized storage elements. |
| 7043611 |
Reconfigurable memory controller |
May 9, 2006 |
| A reconfigurable memory controller includes a plurality of communicatively coupled memory controllers. The plurality of memory controllers may be configured into a first configuration based on a grouping of memory controllers and then reconfigured into a second configuration based on a |
| 7043591 |
Cross switch supporting simultaneous data traffic in opposing directions |
May 9, 2006 |
| An apparatus comprising a first bus segment, a second bus segment and a switch. The first bus segment may be configured to transfer data in either a first direction or a second direction. The second bus segment may be configured to transfer data in either the first direction or the s |
| 7043416 |
System and method for state restoration in a diagnostic module for a high-speed microprocessor |
May 9, 2006 |
| A system and method are presented for saving and restoring the state of a diagnostic module in a microprocessor. The diagnostic module contains a complex break state machine, capable of halting the microprocessor at specified breakpoints. These breakpoints are based on combinations of |
| 7042971 |
Delay-locked loop with built-in self-test of phase margin |
May 9, 2006 |
| A method and apparatus for measuring phase margin of a delay-locked loop (DLL) is provided in which a reference clock is applied to a reference input of the DLL. An auxiliary variable delay is coupled within the DLL and is varied until the DLL becomes unstable. A phase margin output is |
| 7042899 |
Application specific integrated circuit having a programmable logic core and a method of operati |
May 9, 2006 |
| The present invention provides an application specific integrated circuit and a method of operation thereof. In one advantageous embodiment, the application specific integrated circuit includes a programmable logic core having an array of dynamically configurable arithmetic logic units. |
| 7042747 |
Ternary CAM bitcells |
May 9, 2006 |
| Two new ternary CAM bitcell design options are presented that provide compact layout solutions while maximizing matchline channels routing through the cells. In both layouts, the first inventive layout, an asymmetric layout of the 6T-SRAM bitcell is used to improve ease of layout, de |
| 7042737 |
System for efficiently channeling high frequency data signals through sheet metal containment |
May 9, 2006 |
| A system is provided for channeling high frequency signals through sheet metal containment within an electronic device. In exemplary embodiments of the invention, an electronic device employing the system includes a midplane circuit board. One or more interface modules may be coupled to |
| 7042717 |
Data storage system with a removable backplane having a array of disk drives |
May 9, 2006 |
| An array of disk drives may be mounted onto a backplane that may slide as a single unit into an enclosure, such as a rack mounted enclosure. The backplane may allow the disk drives to be arranged in multiple columns and rows such that the disk drives are generally parallel to each other. |
| 7042296 |
Digital programmable delay scheme to continuously calibrate and track delay over process, voltag |
May 9, 2006 |
| The method and circuit of the present invention compensates a timing change over PVT variations without adverse impact on the system. The method and circuit uses two digital programmable delay circuits which have a Master/Slave relationship. The master programmable delay circuit trac |
| 7042242 |
Built-in self test technique for programmable impedance drivers for RapidChip and ASIC drivers |
May 9, 2006 |
| A circuit which includes the addition of test points and analog circuitry required to perform a four-point measurement technique. Test points are fed to an analog multiplexer which is under control of test logic added to the design to facilitate the testing. The output of the analog |
| 7041516 |
Multi chip module assembly |
May 9, 2006 |
| A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. Th |
| 7039896 |
Gradient method of mask edge correction |
May 2, 2006 |
| The present invention is directed to a method and apparatus for making mask edge corrections using a gradient method for high density chip designs. The present invention uses a newly defined cost function. |
| 7039891 |
Method of clock driven cell placement and clock tree synthesis for integrated circuit design |
May 2, 2006 |
| A method of cell placement and clock tree synthesis includes steps of: (a) identifying critical paths in an integrated circuit design; (b) partitioning the integrated circuit design into a timing group for each of the critical paths; (c) assigning each flip-flop in a critical path to |
| 7039855 |
Decision function generator for a Viterbi decoder |
May 2, 2006 |
| A decision function generator for a Viterbi decoder includes a compressor module for receiving arguments of a decision function and for evaluating functions of the arguments of the decision function, a memory module coupled to the compressor module for generating an intermediate function |
| 7039829 |
Apparatus and method for enhancing data availability by implementing inter-storage-unit communic |
May 2, 2006 |
| An apparatus and method for enhancing data availability by implementing inter-storage-unit communication in a data processing system. A Remote Volume Mirroring (RVM) system may be leveraged according to the present invention to provide volume failover by enhancing the functionality of |
| 7039799 |
Methods and structure for BIOS reconfiguration |
May 2, 2006 |
| Methods and structure for customizable BIOS in a peripheral device adapter. The controller of a peripheral device adapter senses a selection indicative of a desired customized BIOS configuration. BIOS information is updated to reflect the desired customized selection. In one embodime |
| 7039756 |
Method for use of ternary CAM to implement software programmable cache policies |
May 2, 2006 |
| A method of operating a circuit is disclosed. The method generally comprises the steps of (A) generating a particular policy of a plurality of policies by a lookup operation on a first transaction request received by the circuit, (B) generating a second transaction request for use by a |
| 7039556 |
Substrate profile analysis |
May 2, 2006 |
| A system for analyzing fabrication processes, such as analyzing device yield on a substrate. An input accesses fabrication information, where the fabrication information includes at least one of an dependent variable that is associated with substrate location information, and at leas |
| 7039298 |
Extraction of audio/visual segment from digital versatile disk content |
May 2, 2006 |
| A segment of audio/visual (A/V) content is extracted from the overall DVD content of a DVD program or disk. A DVD player with A/V segment extraction functionality receives commands from a user that identify start and stop points in the DVD content for the desired A/V segment and that |
| 7039169 |
Detection and authentication of multiple integrated receiver decoders (IRDs) within a subscriber |
May 2, 2006 |
| Apparatus and methods that allow detection and authentication of multiple devices within a subscriber dwelling. A system is described generally comprising multiple devices, each adapted to receive a broadband signal and including a modem coupled to a telephone line. At least one of the |
| 7039064 |
Programmable transmission and reception of out of band signals for serial ATA |
May 2, 2006 |
| An apparatus generally comprising a plurality of writeable registers, a control circuit, and a transmitter circuit. The writeable registers may be configured to store (i) a first burst value and (ii) a first gap value. The control circuit may be configured to generate an idle signal |
