| Patent Number |
Title Of Patent |
Date Issued |
| 6873948 |
Method and apparatus for emulating a device within a data processing system |
March 29, 2005 |
| A method and apparatus in a data processing system for mimicking a device attached to a bus. Signaling is detected on the bus indicating a request to access the device. The bus is then monitored for a response by the device. If a selected period of time passes without a response being ma |
| 6872612 |
Local interconnect for integrated circuit |
March 29, 2005 |
| An integrated circuit having a gate region, a source drain region, and an electrically nonconductive spacer separating the gate region and the source drain region. A local interconnect electrically connects the gate region to the source drain region across the electrically nonconductive |
| 6872321 |
Direct positive image photo-resist transfer of substrate design |
March 29, 2005 |
| A method of forming a photo-resist image on a substrate, such as a conductive film. The method provides that a photo-resist image is printed directly onto the conductive film, such as by using an ink jet printer. Specifically, a CAD image may be sent from a computer to the ink jet pr |
| 6871333 |
Bent gate transistor modeling |
March 22, 2005 |
| A method of characterizing a total width and an overall effective length for a bent gate. The bent gate is divided into logical portions, and each of the logical portions is designated as one of a bent portion, a corner portion, and a straight portion. A corner portion gate width and a c |
| 6871316 |
Delay reduction of hardware implementation of the maximum a posteriori (MAP) method |
March 22, 2005 |
| A decoder generally comprising a branch metrics circuit and a state metrics circuit. The branch metrics circuit may be configured to generate a plurality of branch metric signals. The state metrics circuit may be configured to (i) add the branch metric signals to a plurality of state |
| 6871297 |
Power-on state machine implementation with a counter to control the scan for products with hard- |
March 22, 2005 |
| An apparatus comprising a controller circuit and a BISR assembly circuit. The controller circuit may be configured to present one or more control signals. The control signals may be configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of o |
| 6871249 |
PCI-X 2.0 receiver with initial offset for biased idle transmission line |
March 22, 2005 |
| A receiver with initial offset for biased idle transmission line suitable for providing a programmable amount of initial offset. The receiver comprises a standard differential receiver and one or more initial offset modules. Each initial offset module includes a transistor and two or mor |
| 6871247 |
Mechanism for supporting self-modifying code in a harvard architecture digital signal processor |
March 22, 2005 |
| For use in a processor having separate instruction and data buses, separate instruction and data memories and separate instruction and data units, a mechanism for, and method of, supporting self-modifying code and a digital signal processor incorporating the mechanism or the method. In o |
| 6871154 |
Method and apparatus for automatically configuring and/or inserting chip resources for manufactu |
March 22, 2005 |
| The present invention is directed to a method and an apparatus for automatically configuring and/or inserting chip resources for manufacturing tests. A maximum test configuration ("test backplane") for all IP blocks is created and loaded into a tool suite. When a user issues a reques |
| 6870928 |
Line interface, apparatus and method for coupling transceiver and transmission line |
March 22, 2005 |
| A line interface couples signals between a data transceiver and a transmission line having a load impedance Z. The line interface includes a transformer, a driver circuit for supplying a transmit signal from the data transceiver to the transformer, and a receiver circuit for receiving |
| 6870838 |
Multistage digital cross connect with integral frame timing |
March 22, 2005 |
| A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized |
| 6870782 |
Row redundancy memory repair scheme with shift to eliminate timing penalty |
March 22, 2005 |
| A memory having built-in self repair with row shifting is provided. The rows in the memory are divided into smaller row groups and a bad row group is repaired with a redundant row group. Each row group receives a row select signal, which is fed into a shift circuit for the row group and |
| 6870386 |
Method and apparatus for measuring sheet resistance |
March 22, 2005 |
| A resistance measurement circuit includes a plurality of current sources, a plurality of resistor strings and a comparator. Each resistor string is coupled in series with a respective one of the current sources and includes a plurality of nodes with different resistances relative to a |
| 6870160 |
Method and apparatus for monitoring the condition of a lubricating medium |
March 22, 2005 |
| An apparatus for monitoring the condition of a lubricating medium includes a UV light source, a UV receiver, a processor electrically coupled to both the UV light source and the UV receiver, and a memory device electrically coupled to the processor. The memory device has stored therein a |
| 6869893 |
Laminate low K film |
March 22, 2005 |
| Application of an extremely low K material by the application of a laminate onto a wafer. The laminate preferably contains alternating layers of low K material and etch stop layers, and could be applied by rolling the laminate onto the wafer. An anneal process can be utilized to bond the |
| 6868536 |
Method to find boolean function symmetries |
March 15, 2005 |
| The present invention is directed to a system and method of finding Boolean symmetries. In aspects of the present invention, a method, system and computer-readable medium constructs a symmetry tree for any Boolean function. A data structure which describes groups of commutative variables |
| 6868535 |
Method and apparatus for optimizing the timing of integrated circuits |
March 15, 2005 |
| Integrated circuits are designed having optimal signal timing between and among cells. A set of identities are generated corresponding to logic operations and to library cells in technology basis. A resynthesis window is created for the identities having less than a predetermined depth o |
| 6868492 |
Methods and apparatus for booting a host adapter device devoid of nonvolatile program memory |
March 15, 2005 |
| Methods and associated structure for booting host adapter devices in a system where the host adapter devices are devoid of independent, nonvolatile memory devices for storage of programmed instructions operable within the intelligent host adapter device. The operational programmed in |
| 6868459 |
Methods and structure for transfer of burst transactions having unspecified length |
March 15, 2005 |
| Methods and associated structure for providing a substitute, predetermined, fixed length when transferring burst transactions from one device to another through a bridge device where the burst transaction has an indefinite length specified. In one exemplary preferred embodiment, an A |
| 6868355 |
Automatic calibration of a masking process simulator |
March 15, 2005 |
| A method and system is provided for automatically calibrating a masking process simulator using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected. Data |
| 6867488 |
Thick metal top layer |
March 15, 2005 |
| An integrated circuit having signal traces, power traces, and ground traces. The signal traces are disposed on at least one signal distribution layer, and the signal traces on the at least one signal distribution layer are formed at no more than a first thickness. The power traces and gr |
| 6867480 |
Electromagnetic interference package protection |
March 15, 2005 |
| A method of shielding an integrated circuit from electromagnetic interference. The integrated circuit is at least partially encapsulated within an electromagnetic interference resistant molding compound, and then the integrated circuit is completely encapsulated within a second moldi |
| 6867127 |
Diamond metal-filled patterns achieving low parasitic coupling capacitance |
March 15, 2005 |
| Provided are methods and composition for forming diamond metal-filled patterns above an integrated circuit substrate. A metal layer is formed above the integrated circuit substrate, which is then patterned such that a metal line is created. A plurality of diamond-shaped metal regions are |
| 6866970 |
Apparatus and method to improve the resolution of photolithography systems by improving the temp |
March 15, 2005 |
| A mask for use in a photolithographic process. The mask includes a plate or substrate having first and second opposite surfaces, a first image on the first surface of the substrate and a second image on the second surface of the substrate. When the mask is used in a photolithographic pro |
| 6865435 |
Method of translating a net description of an integrated circuit die |
March 8, 2005 |
| A method of representing a net includes steps of: (a) receiving as input vertices of a net in an integrated circuit die; (b) calculating rounded coordinates having a selected resolution for each of the vertices; (c) calculating rounded coordinates having the selected resolution along the |
| 6865220 |
System and method for implementing an end-to-end error-correcting protocol in a voice band data |
March 8, 2005 |
| A system and method to establish an end-to-end error correcting protocol between two voice band data modems over a network including voice band data relay gateways, where part of the end-to-end connection is via low data rate narrowband network. Using a partial implementation of V.42 LAP |
| 6865189 |
Minimal latency serial media independent interface to media independent interface converter |
March 8, 2005 |
| A method for reducing latency in conversions from a SMII (Serial Media Independent Interface) to a MII (Media Independent Interface). The method involves generating receive and transmit clock signals from a physical layer device; generating receive and transmit clock signals at a media |
| 6865173 |
Method and apparatus for performing an interfrequency search |
March 8, 2005 |
| The present invention a system and method are provided for performing an inter-frequency search with reduced loss of link frames in a CDMA system. The CDMA system includes a base station (20) and a mobile station (50). The mobile station (50) has a searcher (164), which searches for pilo |
| 6864748 |
Differential current amplifier with common mode rejection and high frequency boost |
March 8, 2005 |
| An amplifier for a differential signal drain is able to amplify a signal over a frequency range and boost the signal within a specified frequency range. A resistor is placed between the drain and gate of the first transistor of a cascode amplifier and can be selected to provide addit |
| 6864716 |
Reconfigurable memory architecture |
March 8, 2005 |
| A pre-diffused high density array of core memory cells is provided in a metal programmable device. The peripheral logic is made up of gate array cells in the metal programmable device. The peripheral logic may be configured to access the core memory cells as various memory types, wid |
| 6864563 |
Grounding mechanism for semiconductor devices |
March 8, 2005 |
| A configuration including a grounding mechanism protects a semiconductor device from electrical overstress damage during processes, such as an RIE process, where an electrical charge can build up on the semiconductor device. According to an exemplary embodiment, the configuration secures |
| 6864152 |
Fabrication of trenches with multiple depths on the same substrate |
March 8, 2005 |
| Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow tren |
| 6864141 |
Method of incorporating nitrogen into metal silicate based dielectrics by energized nitrogen ion |
March 8, 2005 |
| A method of making a thin gate dielectric includes providing a metal silicate on a silicon substrate. Nitrogen is implanted into the metal silicate. |
| 6864020 |
Chromeless phase shift mask using non-linear optical materials |
March 8, 2005 |
| An attenuated phase shift mask is formed using a non-linear optical material for both fiducial features and pattern features. The non-linear optical material selected has predetermined transmission at the actinic exposure wavelength and a smaller transmission at the fiducial recognition |
| 6862671 |
System and method for optimizing establishment of mirrored data |
March 1, 2005 |
| The present invention is directed to a system and method for optimizing establishment of mirrored data. In an aspect of the present invention, a method of tracking changes to mirrored storage system including a first storage device and a second storage device may include creating a map |
| 6862296 |
Receive deserializer circuit for framing parallel data |
March 1, 2005 |
| A receive deserializer circuit which frames parallel data utilizes a skip-bit technique for aligning a predefined data reference pattern with a word clock. The receive deserializer circuit includes a sampling flip flop which receives serial data including a data reference pattern. The |
| 6861864 |
Self-timed reliability and yield vehicle array |
March 1, 2005 |
| A test vehicle a system and method for evaluating an interconnect module manufacturing process while dynamically testing performance with high-speed operational frequencies is disclosed. An interconnect module designed at many of the manufacturing process limits offers complete and f |
| 6861748 |
Test structure |
March 1, 2005 |
| A test structure for an integrated circuit having a first underlying conductive layer. A first nonconductive layer is disposed over the first underlying conductive layer, and a first overlying conductive layer is disposed over the first nonconductive layer. First conductive vias form |
| 6861739 |
Minimum metal consumption power distribution network on a bonded die |
March 1, 2005 |
| A method for minimum metal consumption power distribution includes the steps of forming a circuit having a plurality of circuit components on an electrically insulated substrate and forming a plurality of supply voltage regulators on the electrically insulating substrate wherein each of |
| 6861310 |
Capacitor having a tantalum lower electrode and method of forming the same |
March 1, 2005 |
| A capacitor has a titanium nitride layer deposited on a silicon substrate for stress reduction and adherence promotion, and a layer of tantalum is deposited thereon. The tantalum layer is oxidized to produce a tantalum pentoxide layer. A top electrode of metal or polysilicon is then depo |
| 6861183 |
Scatter dots |
March 1, 2005 |
| A mask used for imaging nearly dense features in a substrate. Scatter dots are disposed on the mask in proximity to the nearly dense features, where the scatter dots adjust photon levels of the nearly dense features to a desired level. The adjustment is controlled by selective adjustment |
| 6859890 |
Method for reducing data/parity inconsistencies due to a storage controller failure |
February 22, 2005 |
| A method for reducing data/parity inconsistencies due to a storage controller failure in computer storage systems with dual, independent storage controllers and a number of logical volumes comprising one or more physical disk drive devices includes recognizing a failure of the storage |
| 6859886 |
IO based embedded processor clock speed control |
February 22, 2005 |
| An input/output controller that allows independent and configurable reduction of clock speeds to its embedded processors when they are not in use to save average power consumption. The processor clock speeds are restored when new input/output requests are received. |
| 6859609 |
Portable digital recorder |
February 22, 2005 |
| A method and apparatus for recording digital video and/or audio signals include input audio and video interfaces, a memory, a video frame selector, and output audio and video interfaces. In an alternate embodiment, the method and apparatus include input audio and video interfaces, a |
| 6858930 |
Multi chip module |
February 22, 2005 |
| A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of t |
| 6858531 |
Electro chemical mechanical polishing method |
February 22, 2005 |
| Embodiments of the invention include a method for electro chemical mechanical polishing of a substrate. The process includes flowing an electro chemical mechanical polishing (ECMP) slurry having a high viscosity with a polishing agent over a portion of the substrate. Electrical curre |
| 6858195 |
Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide diele |
February 22, 2005 |
| The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes that include one or more organofluoro silanes selected from: (a) an organofluoro silane containing two silicon |
| 6857108 |
Interactive representation of structural dependencies in semiconductor design flows |
February 15, 2005 |
| The present invention is directed to an interactive representation of structural dependencies in semiconductor design flows. In an aspect of the present invention, a method for providing interactive representation of structural dependencies in a semiconductor design flow as implemented b |
| 6857084 |
Multiprocessor system and method for simultaneously placing all processors into debug mode |
February 15, 2005 |
| Multiple processors of a multiprocessor system are placed into a debug mode of operation approximately simultaneously when one processor initially enters the debug mode as a result of incurring a debug event. The other processors enter the debug mode as a result of the one processor asse |
| 6856029 |
Process independent alignment marks |
February 15, 2005 |
| An integrated circuit substrate having a first surface for receiving a series of aligned layers during the creation of the integrated circuit, and a second surface disposed substantially opposite the first surface, where the second surface has at least one alignment mark for aligning the |
