| Patent Number |
Title Of Patent |
Date Issued |
| 6961786 |
Fiber loop linking/detecting |
November 1, 2005 |
| A mechanism is provided for detecting new devices added to a Fiber Channel adapter. When a device is added to a connector, the mechanism generates a device detect signal for that port. The Fiber controller receives device detect signals for the existing ports and generates port select si |
| 6961514 |
System and method for communicating images to a removable media device |
November 1, 2005 |
| A system and method for communicating an image to a removable media device includes communicating the image from an image capture device to the removable media device over a wireless connection. The communicated image is stored in memory on the removable media device, and the stored imag |
| 6960979 |
Low temperature coefficient resistor |
November 1, 2005 |
| A resistor having a desired temperature coefficient of resistance and a total electrical resistance. A first resistor segment has a first temperature coefficient of resistance and a first electrical resistance. A second resistor segment has a second temperature coefficient of resistance |
| 6959428 |
Designing and testing the interconnection of addressable devices of integrated circuits |
October 25, 2005 |
| A register address generation tool is used during the design of semiconductor products. For those registers and/or memories that are addressable on a bus, the register address generation tool creates the interconnect RTL, header files, static timing analysis constraint files, and ver |
| 6959413 |
Method of handling unreadable blocks during rebuilding of a RAID device |
October 25, 2005 |
| Disclosed is a method for continuing a rebuilding process of a RAID system by flagging a block of data as being bad when a media error or other error occurs that prohibits the reconstruction of data. The block of data may be flagged by writing a bad error correction code to the block of |
| 6959376 |
Integrated circuit containing multiple digital signal processors |
October 25, 2005 |
| The present invention is an integrated circuit containing multiple digital signal processors (DSPs). A single host processor interface is also placed on the chip to connect the multiple DSPs to the host. A separate direct memory access (DMA) unit is provided for each DSP to facilitate fl |
| 6959258 |
Methods and structure for IC temperature self-monitoring |
October 25, 2005 |
| Methods and systems are provided for thermal self-monitoring of integrated circuits. Temperature is sensed, digitized, encoded, and compared to one or more threshold values by circuits added within an integrated circuit. A signal produced by a thermal diode within an integrated circuit i |
| 6959007 |
High speed network protocol stack in silicon |
October 25, 2005 |
| An apparatus comprising a media access controller (MAC), a configurable packet switch, and a network protocol stack in silicon. The network protocol stack may be configured to couple the media access controller to the configurable packet switch. |
| 6958541 |
Low gate resistance layout procedure for RF transistor devices |
October 25, 2005 |
| A region on a substrate contains multiple transistors in parallel that share a single salicided polysilicon gate electrode. Above or below the gate electrode are formed multiple plugs of refractory material along the length of the gate electrode. The multiple plugs of refractory material |
| 6957279 |
Selectable logical identifier mapping |
October 18, 2005 |
| The present invention is directed to a configurable input/output interface and method for data transfer between a host and a target in a network environment. A method for providing data transfer between a host and a target in a network environment by a configurable input/output interface |
| 6957162 |
Low-impact analyzer interface |
October 18, 2005 |
| Disclosed is a method and apparatus for providing a universal SCSI bus interface in which bus performance is not degraded, and the analyzer is not negatively influenced by post processing while maintaining the ability to filter and store data using any of a number of generic logic analyz |
| 6956788 |
Asynchronous data structure for storing data generated by a DSP system |
October 18, 2005 |
| In some embodiments, a system includes a memory device in a first clock domain region and a memory device and a digital signal processing (DSP) sub-system in a second clock domain region. In addition, a plurality of asynchronous first-in first-out (FIFO) data structures, each comprising |
| 6955937 |
Carbon nanotube memory cell for integrated circuit structure with removable side spacers to perm |
October 18, 2005 |
| A carbon nanotube memory cell for an integrated circuit wherein a chamber is constructed in a layer of a dielectric material such as silicon nitride down to a first electrical contact. This chamber is filled with polysilicon. A layer of a carbon nanotube mat or ribbon is formed over the |
| 6954810 |
Transparent switch |
October 11, 2005 |
| A transparent switch is able to emulate the arbitration and addressing steps for devices that are normally connected to a bus-type communications network. The switch is connected to the devices in a star-type arrangement, with each device connected to a separate port. The switch perf |
| 6954705 |
Method of screening defects using low voltage IDDQ measurement |
October 11, 2005 |
| A method of screening defects includes steps of: (a) measuring a quiescent current at a first supply voltage for each of a plurality of devices; (b) measuring a quiescent current at a second supply voltage for each of the plurality of devices; (c) generating a plot of the quiescent curre |
| 6954107 |
Differential current amplifier with common mode rejection and high frequency boost |
October 11, 2005 |
| An amplifier for a differential signal drain is able to amplify a signal over a frequency range and boost the signal within a specified frequency range. A resistor is placed between the drain and gate of the first transistor of a cascode amplifier and can be selected to provide addit |
| 6954091 |
Programmable phase-locked loop |
October 11, 2005 |
| An integrated circuit is provided, which includes a phase-locked loop (PLL) that is fabricated on the integrated circuit and has a selectable loop filter capacitance and a selectable output frequency range. |
| 6954082 |
Method and apparatus for testing of integrated circuit package |
October 11, 2005 |
| A method and apparatus for testing an integrated circuit (IC) package includes a printed circuit board (PCB) on which is mounted the IC package and which is removably connected (preferably perpendicular) to a motherboard. The IC package, the PCB and the motherboard are subjected to t |
| 6952789 |
System and method for synchronizing a selected master circuit with a slave circuit by receiving |
October 4, 2005 |
| A mechanism for synchronizing a multiple-circuit system, includes (a) selecting a master circuit from a plurality of circuits, the remaining circuits including at least one slave circuit, (b) receiving, at each of the plurality of circuits, input data and a local clock signal associated |
| 6952452 |
Method of detecting internal frame skips by MPEG video decoders |
October 4, 2005 |
| An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) generate a random number signal, (ii) read a data signal, and (iii) generate one or more control signals. The second circuit may be configured to (i) store the random number signal, |
| 6951808 |
Metal planarization system |
October 4, 2005 |
| A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral |
| 6951787 |
Capacitor with stoichiometrically adjusted dielectric and method of fabricating same |
October 4, 2005 |
| A capacitor and a capacitor dielectric material are fabricated by adjusting the amount of an ionic conductive species, such as hydrogen, contained in the capacitor dielectric material to obtain predetermined electrical or functional characteristics. Forming the capacitor dielectric mater |
| 6951017 |
Design system upgrade migration |
September 27, 2005 |
| A software tool is created to migrate computer files that define ICs from older to newer computer-readable directory structures. The old and new directories are compared to identify differences that are mapped and sorted on the basis of directory source names. A computer file defining an |
| 6951000 |
Simulated voltage contrasted image generator and comparator |
September 27, 2005 |
| A method of generating a simulated voltage contrast image includes steps for receiving as input design information for an integrated circuit die, selecting a net of the integrated circuit from the design information, generating a trace outline of the selected net from the image, analyzin |
| 6950352 |
Method and apparatus for replacing a defective cell within a memory device having twisted bit li |
September 27, 2005 |
| A method and apparatus is provided for replacing defective storage cells within a memory device having twisted bit lines. If a defective storage cell is discovered, the row containing that storage cell can be re-mapped to the neighboring row or the memory array. Each successive neighbori |
| 6949446 |
Method of shallow trench isolation formation and planarization |
September 27, 2005 |
| Provided is a technique for fabrication of STIs in a semiconductor device using implantation of damaging high-energy ions to insulating material overburden to generally and/or selectively increase insulation overburden removal rates. This technique avoids the use of chemical mechanical |
| 6948142 |
Intelligent engine for protection against injected crosstalk delay |
September 20, 2005 |
| A method of protecting a net of an integrated circuit against injected crosstalk delay includes receiving a synthesized signal path structure and a value of maximum allowable injected crosstalk delay for a selected net in the signal path structure. The signal path structure is analyzed t |
| 6948139 |
Method for combining states |
September 20, 2005 |
| A method for combining states of a state machine employs manipulation of case statements in the RTL code implementing the state machine to allow selectable state combinations without duplication of code so that errors inherent in maintaining duplicate copies of the same RTL code may be |
| 6948114 |
Multi-resolution Viterbi decoding technique |
September 20, 2005 |
| A method for decoding an encoded signal. A first step generates a plurality of first precision state metrics for a decoder trellis in response to a plurality of first precision branch metrics. A second step generates a plurality of second precision state metrics for a selected subset of |
| 6948054 |
Simple branch prediction and misprediction recovery method |
September 20, 2005 |
| A method of conditional branching in a pipelined processor. The method comprising the steps of (A) prefetching a branch target address in response to encountering a branch instruction, in prediction of taking a branch, and (B) evaluating between (i) taking the branch and (ii) not tak |
| 6948019 |
Apparatus for arbitrating non-queued split master devices on a data bus |
September 20, 2005 |
| A slave device on a data bus has a register that stores a non-queued split master vector containing bits identifying whether a transaction with corresponding master devices have been split. An input gate is responsive to the status of the slave device and to receipt of a command from a |
| 6947056 |
Low power, variable precision DDA for 3D graphics applications |
September 20, 2005 |
| An apparatus generally having a register, an adder circuit and a mask circuit is disclosed. The register may be configured to replace a current value with a new value in response to a clock value. The adder circuit may be configured to generate the new value by adding the current value t |
| 6946866 |
Measurement of package interconnect impedance using tester and supporting tester |
September 20, 2005 |
| A tester head from a tester is used to mount a probe card. A DUT/load board has a socket which is configured to hold a substrate. Probe pins from the probe card make contact with bump pads on the substrate. Signal wires from the DUT/load board are fed to the tester, and the tester is con |
| 6944791 |
Method of handling unreadable blocks during write of a RAID device |
September 13, 2005 |
| Disclosed is a method for continuing a write operation in a RAID device when parity cannot be generated. In cases where a read error or plurality of read errors prohibits the proper calculation of parity for a block of data, the parity block may be written as a bad block of data for |
| 6944712 |
Method and apparatus for mapping storage partitions of storage elements for host systems |
September 13, 2005 |
| System and methods for managing requests of a host system to physical storage partitions. A storage system includes a plurality of storage elements with each storage element configured for providing data storage. A communications switch is communicatively connected to the storage ele |
| 6944152 |
Data storage access through switched fabric |
September 13, 2005 |
| A switched fabric, instead of a shared bus, establishes a data transfer path between a host device and a storage device. The host device accesses data stored on the storage device, but with data transfer speed and bandwidth advantages of a switched fabric architecture over a shared bus |
| 6943633 |
Widely tunable ring oscillator utilizing active negative capacitance |
September 13, 2005 |
| A ring oscillator that uses active negative capacitance at one or more stages of the ring oscillator to adjust the frequency of oscillation. By using a negative capacitance generator, negative capacitance may be placed in shunt with each stage of the ring, thereby reducing the effective |
| 6943446 |
Via construction for structural support |
September 13, 2005 |
| An integrated circuit having electrically conductive vias with a diameter of between about one micron and about fifty microns. Prior art vias have a diameter of between no less than 0.3 microns to no more than 0.8 microns. In this manner, stresses such as those that press down upon the t |
| 6943415 |
Architecture for mask programmable devices |
September 13, 2005 |
| The present invention is directed to a semi-programmable ASIC using two metals for the metal layers. The semi-programmable ASIC may have a prefabricated first section and a customized second section. The prefabricated first section and the customized second section may each include o |
| 6943055 |
Method and apparatus for detecting backside contamination during fabrication of a semiconductor |
September 13, 2005 |
| A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contam |
| 6943042 |
Method of detecting spatially correlated variations in a parameter of an integrated circuit die |
September 13, 2005 |
| A method of detecting spatially correlated variations that may be used for detecting statistical outliers in a production lot of integrated circuits to increase the average service life of the production lot includes measuring a selected parameter of each of a plurality of electronic |
| 6941533 |
Clock tree synthesis with skew for memory devices |
September 6, 2005 |
| A method of synthesizing a clock tree for reducing peak power in an integrated circuit design includes partitioning a circuit design into a set of memory cells and a set of non-memory cells, partitioning the set of memory cells into segments, constructing a first clock tree having a firs |
| 6941494 |
Built-in test for multiple memory circuits |
September 6, 2005 |
| A memory test circuit includes a collar for coupling to a memory device for switching an address bus and a data bus of the memory device between an external circuit and the collar in response to a switching signal; and a controller coupled to the collar for generating the switching signa |
| 6941427 |
Method and apparatus for improving queue traversal time |
September 6, 2005 |
| A method and apparatus for traversing a queue of commands through part or all of the queue by selecting only the commands that need to be reissued. Commands to be reissued are labeled or designated as valid. The method may be practiced by setting a next valid address pointer in all queue |
| 6941408 |
Bus interface system with two separate data transfer interfaces |
September 6, 2005 |
| The present invention is directed to an interface. In an aspect of the present invention, an interface system suitable for coupling a bus interface controller with a back-end device includes a bus interface controller and a back-end device in which the back-end device is coupled to t |
| 6941314 |
User selectable editing protocol for fast flexible search engine |
September 6, 2005 |
| A method of editing a sorted tree data structure includes selecting a minimum number of entries and a maximum number of entries in each vertex of the sorted tree data structure. If inserting an entry into a bottom vertex of the sorted tree data structure exceeds the maximum number of |
| 6940982 |
Adaptive noise cancellation (ANC) for DVD systems |
September 6, 2005 |
| An apparatus comprising an input, a noise cancellation circuit, an audio circuit and a mixing circuit. The input may be configured to receive one or more input signals. The noise cancellation circuit may be configured to generate a first processed audio signal having reduced noise in res |
| 6940909 |
Video decoding during I-frame decode at resolution change |
September 6, 2005 |
| A method of buffering a video signal is disclosed. The method generally includes the steps of (A) storing a plurality of pictures decoded from the video signal having a first resolution in a memory space divided into a plurality of first buffers each having a first size, (B) dividing the |
| 6940790 |
Write compensation for a multi-level data storage system |
September 6, 2005 |
| A system and method are disclosed for compensating during a data writing process for a transformation of input data by an optical disc data storage channel. A write strategy matrix is derived that maps a plurality of input sequences to a plurality of write strategy parameters. The input |
| 6939800 |
Dielectric barrier films for use as copper barrier layers in semiconductor trench and via struct |
September 6, 2005 |
| The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper |
