| Patent Number |
Title Of Patent |
Date Issued |
| RE38900 |
Automating photolithography in the fabrication of integrated circuits |
November 29, 2005 |
| Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulti |
| 7454303 |
System and method for compensating for PVT variation effects on the delay line of a clock signal |
November 18, 2008 |
| The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO(First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Fun |
| 7444459 |
Methods and systems for load balancing of virtual machines in clustered processors using storage |
October 28, 2008 |
| Methods and systems for generating storage related load factor information for load balancing of multiple virtual machines operable in a cluster of multiple physical processors (such as a blade center). Load factor information is generated within a storage system relating to operation of |
| 7440500 |
Supporting motion vectors outside picture boundaries in motion estimation process |
October 21, 2008 |
| An apparatus generally having a first memory and a circuit is disclosed. The first memory may be used for a motion estimation of a current block. The circuit may be configured to (i) determine if a search window for the current block is at least partially outside a boundary of a picture |
| 7434198 |
Method and computer program product for detecting potential failures in an integrated circuit de |
October 7, 2008 |
| A method of detecting potential failures from a corrected mask design for an integrated circuit includes steps of receiving as input a corrected mask design for an integrated circuit, searching the corrected mask design to find a critical edge of a polygon that is closer than a selec |
| 7430700 |
Failure analysis and testing of semi-conductor devices using intelligent software on automated t |
September 30, 2008 |
| The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and resp |
| 7409498 |
Scaled coercion of disk drive capacity |
August 5, 2008 |
| The present invention provides disk coercion by generating coercion percentages or values that can be used to coerce various disks according to each disk's particular labeled size or capacity. In one embodiment, a disk size is received and a base coercion scaling factor is provided such |
| 7405946 |
Ball grid array assignment |
July 29, 2008 |
| A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in first ordered channels of adjacent transmitter differential pairs. High speed receiver contacts are disposed in a |
| 7405476 |
Asymmetric alignment of substrate interconnect to semiconductor die |
July 29, 2008 |
| An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. |
| 7402770 |
Nano structure electrode design |
July 22, 2008 |
| A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a |
| 7400543 |
Metal programmable self-timed memories |
July 15, 2008 |
| A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from |
| 7400179 |
Digital power-on reset |
July 15, 2008 |
| An apparatus comprising a plurality of flip-flops and a compare circuit. The flip-flops may each be configured to (i) receive a clock signal and an input signal and (ii) generate an output signal. The flip-flops may be configured in series such that the output signal of a first of the |
| 7400170 |
Differential current-mode driver with high common-mode range and controlled edge rates |
July 15, 2008 |
| A differential current-mode driver that meets the IEEE 1394 standard employs a wide output range in common-mode voltage, minimizes timing skew over this wide range, and has well-controlled rise/fall times in the edge rates of the digital signals transmitted, within the window specified b |
| 7397401 |
Arithmetic decode without renormalization costs |
July 8, 2008 |
| An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate context information in response to one or more bins on a binary signal. The second circuit may be configured to generate the binary signal in response to (i) one or more input bi |
| 7385927 |
Methods and structure for improved testing of embedded systems |
June 10, 2008 |
| Methods and structure for standardized communication between a test operator, a host system, and an embedded system under test. Test program instructions are designed, written for, and executed on, an embedded system under test in accordance with standard API functions for message ex |
| 7381502 |
Apparatus and method to improve the resolution of photolithography systems by improving the temp |
June 3, 2008 |
| A mask for use in a photolithographic process. The mask includes a plate or substrate having first and second opposite surfaces, a first image on the first surface of the substrate and a second image on the second surface of the substrate. When the mask is used in a photolithographic |
| 7379422 |
Flow control enhancement |
May 27, 2008 |
| A networking/communication chip having a receiving buffer or FIFO whereby it receives data from a data source across a network and transfers the data to a host system. The memory in the host system acts as a logical extension of the receiving buffer in the chip; in this way, the host |
| 7379416 |
Forward packet data channel with parallel sub-packets |
May 27, 2008 |
| A method of time division multiplexing for a forward data packet channel includes encoding parallel data sub-packets into parallel streams of turbo codes; interleaving each of the parallel streams of turbo codes to generate parallel streams of quasi-complementary turbo codes; modulating |
| 7379281 |
Bias for electrostatic discharge protection |
May 27, 2008 |
| An electrostatic discharge protection circuit adapted to reduce an electrostatic discharge event on a line of an integrated circuit. The protection circuit includes an NMOS transistor having a source contact that is electrically connected to the line. A drain contact is electrically |
| 7376541 |
Accurate pin-based memory power model using arc-based characterization |
May 20, 2008 |
| A pin-based memory power modeling method using arc-based characterization includes steps as follows. All power arcs of a memory model are identified and characterized. A power arc is selected from the identified and characterized power arcs. Output bus switching power is computed by |
| 7376260 |
Method for post-OPC multi layer overlay quality inspection |
May 20, 2008 |
| A method for performing post-optical proximity correction (OPC) multi layer overlay quality inspection includes the steps of generating a virtual target mask for a first mask and a second mask overlay using design rules at least partially defining the relationship between the first m |
| 7375570 |
High-speed TDF testing on low cost testers using on-chip pulse generators and dual ATE reference |
May 20, 2008 |
| A circuit which facilitates TDF testing without having to purchase expensive new test equipment, such as a new test platform that is capable of supporting test frequencies well beyond the current 200 MHz limitation. A solution to current TDF testing problems by adding circuitry to th |
| 7375442 |
Interface circuit for providing a computer logic circuit with first and second voltages and an a |
May 20, 2008 |
| A universal interface circuit and an associated method are provided that can supply a computer logic circuit, such as the components mounted upon an adapter card, with first and second inputs having first and second predetermined voltage levels, respectively, based upon power drawn from |
| 7373629 |
Distributed relocatable voltage regulator |
May 13, 2008 |
| An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the integrated circuit (i) |
| 7373622 |
Relocatable built-in self test (BIST) elements for relocatable mixed-signal elements |
May 13, 2008 |
| An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery o |
| 7371659 |
Substrate laser marking |
May 13, 2008 |
| A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower s |
| 7370309 |
Method and computer program for detailed routing of an integrated circuit design with multiple r |
May 6, 2008 |
| A method of routing an integrated circuit design includes steps of receiving as input at least a portion of an integrated circuit design including at least two separate routing rules assigned to the same net for routing the integrated circuit design, formulating a single combined rou |
| 7370257 |
Test vehicle data analysis |
May 6, 2008 |
| A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one embodiment, the process test circuits may be arranged in a matrix format and connected so |
| 7370139 |
Methods and structures for efficient storage of task file information in serial ATA environments |
May 6, 2008 |
| Methods and structures for efficiently storing task file information for a significant number of SATA devices coupled to a SATA storage controller. A RAM memory within the SATA storage controller may store task file information for virtually any number of SATA devices coupled to a SAS |
| 7369743 |
Enhanced personal video recorder |
May 6, 2008 |
| The present invention is directed to a system, software system and method for effectively managing multimedia broadcast presentations. Effective multimedia broadcast data management offers users increased functionality in how they experience multimedia presentations, manage data and cont |
| 7369066 |
Efficient 8.times.8 CABAC residual block transcode system |
May 6, 2008 |
| A circuit generally including a first module, a second module and a third module is disclosed. The first module may be configured to (i) generate a plurality of parsed residual blocks by parsing a plurality of 4.times.4 CAVLC (context-based adaptive variable length coding) residual block |
| 7366862 |
Method and apparatus for self-adjusting input delay in DDR-based memory systems |
April 29, 2008 |
| A method and apparatus are provided for interfacing with a synchronous dynamic memory in which memory commands are provided to the memory. The memory is accessed in response to the memory commands. Read data is captured in a data capture circuit having a delay setting. The delay sett |
| 7365015 |
Damascene replacement metal gate process with controlled gate profile and length using Si.sub.1- |
April 29, 2008 |
| A method of forming a metal gate in a wafer. PolySi.sub.1-xGe.sub.x and polysilicon are used to form a tapered groove. Gate oxide, PolySi.sub.1-xGe.sub.x, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi.sub.1-xGe.sub.x, and ga |
| 7363608 |
Accelerating PCB development and debug in advance of platform ASIC prototype samples |
April 22, 2008 |
| A system and method are provided for accelerating development and debug of a printed circuit board (PCB) designed for use with a platform ASIC in advance of availability of a prototype sample of the platform ASIC. Aspects of the invention include a pin-out adapter card that implements a |
| 7363451 |
Load balancing of disk drives |
April 22, 2008 |
| System and methods are disclosed for load balancing Input/Output (IO) commands to be executed by one or more disk drives from an array of disk drives. Systems and methods disclosed herein use one or more properties, such as disk drive RPM, disk drive cache, command queue lengths, rea |
| 7363423 |
Multiple match detection circuit |
April 22, 2008 |
| Multiple matches of words in a content addressable memory are detected by identifying each match of the input word to a word in the memory, and generating a representation of a relationship OR (x.sub.i AND x.sub.j), where x.sub.i=x.sub.1, x.sub.2, . . . x.sub.N-1, x.sub.j.epsilon.x.s |
| 7362809 |
Computational reduction in motion estimation based on lower bound of cost function |
April 22, 2008 |
| A method for motion estimation comprising the steps of (A) determining whether a cost of encoding one or more prediction parameters for a current search position is less than a current best cost, (B) when the cost of encoding the one or more prediction parameters for the current sear |
| 7362804 |
Graphical symbols for H.264 bitstream syntax elements |
April 22, 2008 |
| An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a decoded video signal and syntax elements in response to an encoded bitstream. The second circuit may be configured to generate one or more overlay images in response to the |
| 7362801 |
Method for accurate estimation of noise for data modems |
April 22, 2008 |
| Noise and signal-to-noise ratio (SNR) estimation are relatively straightforward tasks. However, when SNR is small, systematic errors in measurement may result in over-estimation of SNR, which also occurs during runtime monitoring of SNR. Here, sufficient numbers of bits have been pre |
| 7362770 |
Method and apparatus for using and combining sub-frame processing and adaptive jitter-buffers fo |
April 22, 2008 |
| A method and apparatus for using and combining sub-frame processing and adaptive jitter-buffers for improved voice quality in voice-over-packet networks. Data is placed in a jitter buffer, where the data has a frame-length consisting of a plurality of samples. Some of the samples are |
| 7362767 |
Integrated circuit with on-chip clock frequency matching to upstream head end equipment |
April 22, 2008 |
| One aspect of the present invention concerns a method for controlling the frequency of oscillation of a local clock signal comprising the steps of (A) generating the clock signal in response to a first control signal, (B) generating the first control signal in response to one of a plural |
| 7362376 |
Method and apparatus for video deinterlacing and format conversion |
April 22, 2008 |
| A method for deinterlacing a picture is disclosed. The method generally includes the steps of (A) generating a plurality of primary scores by searching along a plurality of primary angles for an edge in the picture proximate a location interlaced with a field of the picture, (B) gene |
| 7360178 |
Mixed-signal functions using R-cells |
April 15, 2008 |
| A method for producing a chip is disclosed. A first step of the method may include fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step generally inv |
| 7360133 |
Method for creating a JTAG tap controller in a slice for use during custom instance creation to |
April 15, 2008 |
| A method and system is provided for creating a tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool. Aspects of the present invention include during slice creation, using a software tool to create a test access port (TAP) |
| 7358594 |
Method of forming a low k polymer E-beam printable mechanical support |
April 15, 2008 |
| A low-k interconnect dielectric layer is strengthened by forming pillars of hardened material in the low-k film. An E-beam source is used to expose a plurality of pillar locations. The locations are exposed with a predetermined power and exposure time to convert the low-k film in the |
| 7356785 |
Optimizing IC clock structures by minimizing clock uncertainty |
April 8, 2008 |
| A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers |
| 7356743 |
RRAM controller built in self test memory |
April 8, 2008 |
| An RRAM design having linear BIST memory and rectangular BIST memory, the improvement comprising at least one of the linear BIST memory and the rectangular BIST memory formed only of flipflops and logic cells. |
| 7355931 |
Optical disc center error amplitude calibration |
April 8, 2008 |
| A method for calibrating a center error signal in an optical disc system, comprising the steps of (i) measuring a peak-to-peak value of the center error signal, (ii) computing a nominal peak-to-peak value of the center error signal after locking to a particular track of an optical disc, |
| 7354790 |
Method and apparatus for avoiding dicing chip-outs in integrated circuit die |
April 8, 2008 |
| A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integr |
| 7352062 |
Integrated circuit package design |
April 1, 2008 |
| A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the |
