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LSI Logic Corporation Patents
Assignee:
LSI Logic Corporation
Address:
Milpitas, CA
No. of patents:
3667
Patents:












Patent Number Title Of Patent Date Issued
RE38900 Automating photolithography in the fabrication of integrated circuits November 29, 2005
Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulti
8129759 Semiconductor package and method using isolated V.sub.SS plane to accommodate high speed circuit March 6, 2012
Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground
8044437 Integrated circuit cell architecture configurable for memory or logic elements October 25, 2011
An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers.
8043968 Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect struct October 25, 2011
Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrie
8021955 Method characterizing materials for a trench isolation structure having low trench parasitic cap September 20, 2011
Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A
7804167 Wire bond integrated circuit package for high speed I/O September 28, 2010
An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package
7800936 Latch-based random access memory September 21, 2010
A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.
7760578 Enhanced power distribution in an integrated circuit July 20, 2010
An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails
7757024 Dual porting serial advanced technology attachment disk drives for fault tolerant applications July 13, 2010
The present invention is directed to an apparatus capable of dual porting a serial advanced technology attachment (SATA) disk drive in a fault tolerant communication system, such as fiber channel. The dual porting apparatus includes two idle regenerators coupled to two serial master
7751609 Determination of film thickness during chemical mechanical polishing July 6, 2010
A method and apparatus is provided for determining thickness of films or layers during chemical-mechanical planarization/polishing (CMP) of a semiconductor substrate or wafer in situ. The method may be used to determine end-point during CMP especially of oxide films deposited on the
7657774 Low power memory controller with leaded double data rate DRAM package on a two layer printed cir February 2, 2010
An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and fro
7640461 On-chip circuit for transition delay fault test pattern generation with launch off shift December 29, 2009
A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a
7627789 Polymorphic management of embedded devices using web interfaces December 1, 2009
In some embodiments, a method for managing embedded devices may include one or more of the following steps: (a) loading an embedded web server module, (b) loading a first webpage when loading a first embedded module, (c) replacing the first webpage with a second webpage when a second
7617391 Method and apparatus for dynamically selecting one of multiple firmware images for booting an I/ November 10, 2009
A method and apparatus are disclosed in a data processing system for dynamically selecting one of multiple different I/O firmware images for booting a particular I/O controller that is included in the data processing system. Multiple different I/O firmware images are provided. A conf
7601643 Arrangement and method for fabricating a semiconductor wafer October 13, 2009
An arrangement and method for fabricating a semiconductor wafer which utilizes a nonaqueous solvent rinse is disclosed.
7590819 Compact memory management unit September 15, 2009
A memory management unit (MMU) for a device controller that provides enhanced functionality while maintaining a small physical size or footprint, such that the die size required to manufacture the memory management unit circuitry within the device controller integrated circuit device
7582566 Method for redirecting void diffusion away from vias in an integrated circuit design September 1, 2009
A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a seco
7577928 Verification of an extracted timing model file August 18, 2009
A system, apparatus and method for generating and validating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing charac
7576977 Shoulder screw and handle drive mounting system August 18, 2009
A computer storage enclosure may comprise a mounting chassis and a computer drive apparatus. The mounting chassis may have a plurality of computer drive guides, a plurality of cam pins, and a mounting chassis disengagement ramp. The computer drive apparatus may include a computer dri
7574541 FIFO sub-system with in-line correction August 11, 2009
A flow-based FIFO sub-system for a disk formatter in a data processing system that performs data width conversion. The sub-system has a first FIFO unit having a first width interfacing to a first bursting channel, and a second FIFO unit having a second width interfacing to a second b
7574353 Transmit/receive data paths for voice-over-internet (VoIP) communication systems August 11, 2009
The present invention is a method and apparatus in a data processing system that includes a Voice over Internet Protocol (VoIP) communication system for improving transmit and receive data paths. The communication system includes a digital signal processing unit. The digital signal p
7573870 Transmit prioritizer context prioritization scheme August 11, 2009
A method and system prioritizes frames to be transmitted from a local node to a remote node on a Fibre Channel Arbitration Loop. The frames are placed in context queues. Each kind of context queue is assigned a priority. A determination of a set of transmit frame types is made. A use
7571430 Adaptive dispatch table based on templates August 4, 2009
The present invention is directed to a method of an adaptive procedure table which is capable of providing default behaviors for each procedure if a corresponding procedure is not defined or has been removed from a software build. The default behaviors for each procedure may be defined
7571397 Method of design based process control optimization August 4, 2009
The present invention provides a method of design based process control optimization. In an embodiment, the method of design based process control optimization includes creating a circuit layout database including a design rule set. At least one algorithm is employed to query the cir
7571396 System and method for providing swap path voltage and temperature compensation August 4, 2009
The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes compensating the offline data path for voltage and temperature variation. The method fu
7571370 Configurable, fast, 32-bit CRC generator for 1-byte to 16-bytes variable width input data August 4, 2009
A method and circuit for performing CRC calculations permits variable width data input. Preferably, multiple CRC calculations are performed in parallel, each CRC calculation involving a different number of data bits from the data word and terminating within one clock cycle. The CRC p
7568216 Methods for defining and naming iSCSI targets using volume access and security policy July 28, 2009
The present invention is directed to methods for defining and naming iSCSI targets using volume access and security policy. In an exemplary aspect of the present invention, a method for defining an iSCSI target using volume access and security policy may include the following steps. One
7560292 Voltage contrast monitor for integrated circuit defects July 14, 2009
A semiconductor chip is provided which includes active and inactive IP cores. The spaces on the metal layer associated with the inactive IP cores includes voltage contrast inspection structures. The voltage contrast inspection structures serve to provide improved planarization of the
7555688 Method for implementing test generation for systematic scan reconfiguration in an integrated cir June 30, 2009
A method for implementing test generation for systematic scan reconfiguration in an integrated circuit is presented. The method may comprise: defining at least one set of detectable faults; setting an SAS decoder configuration, the SAS decoder configuration including a don't-care bit
7552355 System for providing an alternative communication path in a SAS cluster June 23, 2009
The present invention is directed to a system and method for supporting an alternative peer-to-peer communication over a network in a SAS cluster when a node cannot communicate with another node through a normal I/O bus (Serial SCSI bus). At startup, driver may establish the alternative
7548844 Sequential tester for longest prefix search engines June 16, 2009
The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for outputting a floatin
7542508 Continuous-time decision feedback equalizer June 2, 2009
A continuous-time domain Decision Feedback Equalizer (DFE) for use in a serial communication channel comprises in one embodiment a summer, a decision circuit, a capture flip-flop (FF) and an N-th order active filter. The DFE and its active filter operate in continuous time to give im
7539798 Mitigating performance degradation caused by a sata drive attached to a sas domain May 26, 2009
The present invention provides a device and method for mitigating performance degradation caused by SATA drives attached to a SAS domain. In one of the embodiments of the present invention, a SATA degradation mitigation device ("SDMD") is installed between a SAS domain and one or mor
7535330 Low mutual inductance matched inductors May 19, 2009
Multiple inductor structures and methods for providing low mutual inductance between the inductors are described. In various embodiments of the invention, the polarities of the inductors are positioned such that parasitic mutual inductance is reduced by causing electro-magnetic fields
7529968 Storing RAID configuration data within a BIOS image May 5, 2009
A system, apparatus and method for storing and maintaining drive configuration data related to disk drives within a RAID. In one embodiment of the invention, configuration data is stored external to the disk drives within the RAID. A scan(s) is performed of the RAID disk drive config
7499146 Lithographic apparatus and device manufacturing method, an integrated circuit, a flat panel disp March 3, 2009
The tilt and position of individually controllable element are simultaneously adjusted to allow a greater range of contrasts to be achieved. This can also be used to compensate for cupping of individually controllable elements. Simultaneous adjustment of both the position and tilt of
7496694 Circuit, systems and methods for monitoring storage controller status February 24, 2009
Circuits, systems and methods for improved monitoring of status of a storage controller in a storage system. A monitoring circuit external to the storage controller is adapted to couple to the internal bus structure within the storage controller. The monitoring circuit is adapted to sens
7489609 Advanced high density data write strategy February 10, 2009
A method of writing a mark to an optical disc includes receiving data to be written and generating a control signal for a laser pulse having a melt period that transitions to a growth period wherein the melt period is characterized by a melt power and the growth period is characterized
7480881 Method and computer program for static timing analysis with delay de-rating and clock conservati January 20, 2009
A method and computer program for static timing analysis includes receiving as input minimum and maximum stage delays for two corners of an integrated circuit design. A path slack for a setup timing check is calculated from the minimum and maximum stage delays as a function of net cl
7479703 Integrated circuit package with sputtered heat sink for improved thermal performance January 20, 2009
An integrated circuit package includes an integrated circuit die having a circuit surface and a back surface opposite the circuit surface. A layer of ductile material is deposited on the back surface of the integrated circuit die.
7458060 Yield-limiting design-rules-compliant pattern library generation and layout inspection November 25, 2008
A method and system are provided for analyzing process window compliance of an integrated circuit design. Aspects of the present invention include identifying layout pattern configurations that have process windows that fail to meet respective local performance specifications; searching
7456498 Integrated circuit package and system interface November 25, 2008
A method for enhancing the performance of an IC package and media interface. Adding a fissure to a Flip-Chip type package improves the crosstalk performance of the package for both high and low frequencies. The wall of the fissure can be implemented with a heat spreader layer and can
7454303 System and method for compensating for PVT variation effects on the delay line of a clock signal November 18, 2008
The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO(First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Fun
7444459 Methods and systems for load balancing of virtual machines in clustered processors using storage October 28, 2008
Methods and systems for generating storage related load factor information for load balancing of multiple virtual machines operable in a cluster of multiple physical processors (such as a blade center). Load factor information is generated within a storage system relating to operation of
7440500 Supporting motion vectors outside picture boundaries in motion estimation process October 21, 2008
An apparatus generally having a first memory and a circuit is disclosed. The first memory may be used for a motion estimation of a current block. The circuit may be configured to (i) determine if a search window for the current block is at least partially outside a boundary of a picture
7434198 Method and computer program product for detecting potential failures in an integrated circuit de October 7, 2008
A method of detecting potential failures from a corrected mask design for an integrated circuit includes steps of receiving as input a corrected mask design for an integrated circuit, searching the corrected mask design to find a critical edge of a polygon that is closer than a selec
7430700 Failure analysis and testing of semi-conductor devices using intelligent software on automated t September 30, 2008
The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and resp
7409498 Scaled coercion of disk drive capacity August 5, 2008
The present invention provides disk coercion by generating coercion percentages or values that can be used to coerce various disks according to each disk's particular labeled size or capacity. In one embodiment, a disk size is received and a base coercion scaling factor is provided such
7405946 Ball grid array assignment July 29, 2008
A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in first ordered channels of adjacent transmitter differential pairs. High speed receiver contacts are disposed in a
7405476 Asymmetric alignment of substrate interconnect to semiconductor die July 29, 2008
An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die.

 
 
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