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LSI Corporation Patents
Assignee:
LSI Corporation
Address:
Milpitas, CA
No. of patents:
1172
Patents:












Patent Number Title Of Patent Date Issued
RE41516 Socketless/boardless test interposer card August 17, 2010
An interposer card used during qualification tests on integrated circuit packages is disclosed that eliminates the need for sockets and custom boards. The interposer card includes pads for mounting the I/Os of a test package; edge card connectors for connecting the interposer card direct
8589853 Total power optimization for a logic integrated circuit November 19, 2013
A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power r
8589722 Methods and structure for storing errors for error recovery in a hardware controller November 19, 2013
Methods and structure for providing methods and structure for recovering errors in a hardware controller after an overwrite event, such as the detection of another error. In this regard, a link layer of the hardware controller is configured with a register that persistently stores errors
8589607 Methods and structure for hardware management of serial advanced technology attachment (SATA) DM November 19, 2013
Methods and structure for enhanced SAS expander functionality to store and forward buffered information transmitted from a SATA end device to an STP initiator device while managing use of Non-Zero Offset ("NZO") field values in DMA Setup FISs transmitted by the SATA end device. The enhan
8588290 Adaptation of crossing latch threshold November 19, 2013
An apparatus including a bang-bang clock and data recovery module and a decision feedback equalizer. The decision feedback equalizer is coupled with the bang-bang clock and data recovery module. The apparatus is configured to reduce an effect on a settling point of the bang-bang clock
8588223 Multi-stage interconnection networks having smaller memory requirements November 19, 2013
In one embodiment, a multistage interconnection network (MIN) has two or more configurable stages, each stage having a plurality of switches. The network has one or more unused input terminals, each mapped using fixed switch connections to an unused output terminal. The network also has
8588024 Static memory with segmented clear November 19, 2013
A static memory system with multiple memory cell that, in response to a reset signal, simultaneously resets or clears a segment of the memory cells in the memory. Clearing the entire memory or a portion thereof is accomplished by sequencing though a subset of address bits while asser
8588004 Memory device having multi-port memory cell with expandable port configuration November 19, 2013
A memory device includes a memory array comprising a plurality of memory cells. At least one of the memory cells comprises a pair of cross-coupled inverters, and a plurality of ports, including at least one write port. A given write port comprises at least one drive control circuit havin
8587888 Methods and apparatus for synchronization mark detection based on a position of an extreme dista November 19, 2013
Methods and apparatus are provided for detection of a synchronization mark based on a position of an extreme distance metric. A synchronization mark is detected in a received signal by computing a distance metric between the received signal and an ideal version of the received signal
8584068 Timing violation debugging inside place and route tool November 12, 2013
A storage medium for use in a computer to develop a circuit design. The storage medium recording a software tool that may be readable and executable by the computer. The software tool generally includes the steps of (A) receiving a first user input that identifies a specific cell of
8583993 Turbo parallel concatenated convolutional code implementation on multiple-issue processor cores November 12, 2013
An iterative PCCC encoder includes a first delay line operative to receive at least one input data sample and to generate a plurality of delayed samples as a function of the input data sample. The encoder further includes a second delay line including a plurality of delay elements co
8583973 Stored-pattern logic self-testing with serial communication November 12, 2013
An integrated circuit chip that supports stored-pattern (SP) logic built-in self-testing (LBIST) includes a device under test (DUT) and a test controller. System-level SP LBIST testing is performed using an external, system ATE (automated test equipment) that transmits test input dat
8583966 Methods and structure for debugging DDR memory of a storage controller November 12, 2013
Methods and structure for diagnosing errors in the initialization of DDR memory "on board" a storage controller or a storage expander are presented herein. The features and aspects discussed herein allow for the debugging of the DDR memory initialization. A memory diagnostic system is
8583874 Method and apparatus for caching prefetched data November 12, 2013
A method is provided for performing caching in a processing system including at least one data cache. The method includes the steps of: determining whether each of at least a subset of cache entries stored in the data cache comprises data that has been loaded using fetch ahead (FA);
8583844 System and method for optimizing slave transaction ID width based on sparse connection in multil November 12, 2013
A system and method for optimizing slave transaction ID width based on sparse connection between multiple masters and multiple slaves in a multilayer multilevel interconnect system-on-chip (SOC) architecture are disclosed. In one embodiment, slave transaction ID widths are computed f
8583840 Methods and structure for determining mapping information inconsistencies in I/O requests genera November 12, 2013
Methods and structure are disclosed for improved processing of fast path I/O requests in a storage controller utilizing version information embedded in the fast path I/O requests. The version information allows the storage controller to determine if the mapping information utilized b
8583839 Context processing for multiple active write commands in a media controller architecture November 12, 2013
Described embodiments provide a method of transferring data from host devices to a media controller. The media controller generates a transfer context for each write request received from a host device. Receive-data threads corresponding to data transfer contexts for each transfer contex
8582635 Sparse and reconfigurable floating tap feed forward equalization November 12, 2013
In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in
8581832 Illumination device having user-controllable light sequencing circuitry configured to select a l November 12, 2013
An illumination device comprises a plurality of light sources, light sequencing circuitry coupled to the light sources, a light guide structure for directing light from the plurality of light sources over a surface of a display screen to be illuminated, and a user interface for provi
8580621 Solder interconnect by addition of copper November 12, 2013
A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electroni
8578473 Systems and methods for information security using one-time pad November 5, 2013
A method of verifying a password and methods of encryption and decryption using a key generated from a one-time pad. In one embodiment, the method of verifying includes: (1) receiving a password attempt, (2) retrieving a pointer from memory, (3) searching a one-time pad based on the poin
8578253 Systems and methods for updating detector parameters in a data processing circuit November 5, 2013
Various embodiments of the present invention provide systems and methods for updating detector parameters in a data processing circuit. For example, a data processing circuit is disclosed that includes a first detector circuit, a second detector circuit, and a calibration circuit. Th
8578241 Systems and methods for parity sharing data processing November 5, 2013
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a low density parity check data decoder circuit, and a processing circuit. The processing circuit is
8578146 Systems and methods for booting a bootable virtual storage appliance on a virtualized server pla November 5, 2013
One embodiment is a method for booting a bootable virtual storage appliance on a virtualized server platform. One such method comprises: providing a virtual storage appliance on a server platform, the virtual storage appliance configured to manage a disk array comprising a plurality
8577402 Method for avoiding overflow of multiplication of roots-of-unity by using overflow safe approxim November 5, 2013
An apparatus including a processor, a computer readable storage medium, and a lookup memory. The computer readable storage medium generally contains computer executable instruction that when executed by the processor perform operations involving fixed point multiplication. The lookup
8576862 Root scheduling algorithm in a network processor November 5, 2013
Described embodiments provide for arbitrating between nodes of scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The
8572543 Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fa October 29, 2013
A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to ce
8572526 Power mesh for multiple frequency operation of semiconductor products October 29, 2013
A semiconductor platform for implementing multiple-frequency operations includes multiple physical resources comprising embedded functions and a configurable transistor fabric. The transistor fabric includes at least first and second portions, the first portion being programmable to
8566816 Code synchronization October 22, 2013
Disclosed is a system and method that resolves a mismatch between software versions executing on redundant controllers. A mismatch between a first software version executing on a first redundant controller and a second software version executing on a second redundant controller is id
8566769 Method and apparatus for generating memory models and timing database October 22, 2013
A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization
8566686 System and method for optimizing read-modify-write operations in a RAID 6 volume October 22, 2013
A method is disclosed for updating parity information in a RAID 6 system wherein only one parity block is read during each write operation. Both parity blocks may be updated from the new data, the data being overwritten and either of the old blocks of parity information. A method for
8566673 Method for improving performance in RAID systems October 22, 2013
A method for computing and storing parity information in a RAID system includes dividing each segment in a stripe into a data block and a parity block, and storing in each parity block, parity information for a limited number of other data blocks in the stripe. A method for rebuilding da
8566666 Min-sum based non-binary LDPC decoder October 22, 2013
Various embodiments of the present invention provide systems and methods for min-sum based decoding of non-binary LDPC codes. For example, a non-binary low density parity check data decoding system is discussed that includes a variable node processor and a check node processor. The v
8566665 Systems and methods for error correction using low density parity check codes using multiple lay October 22, 2013
Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matri
8566658 Low-power and area-efficient scan cell for integrated circuit testing October 22, 2013
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial s
8566635 Methods and systems for improved storage replication management and service continuance in a com October 22, 2013
Systems and methods for management of replicated storage. Features and aspects hereof provide management of data replication among a plurality of storage systems in a manner substantially transparent to host systems attached to the storage systems. The storage systems are coupled to one
8566496 Data prefetch in SAS expanders October 22, 2013
A SAS expander collects data access information associated with a nexus and determines whether a data prefetch is appropriate. The SAS expander identifies potential data blocks utilizing previous data requests of the nexus. The SAS expander issues a data request to the target for the
8566381 Systems and methods for sequence detection in data processing October 22, 2013
Various embodiments of the present invention provide systems and methods for sequence detection. As an example, a method for data detection is disclosed that includes: receiving a series of data samples at a detector circuit; multiplying a portion of the series of data samples by a first
8566379 Systems and methods for self tuning target adaptation October 22, 2013
Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit, a noise predictive filter circuit, a data detector circuit, a data reconstruction circuit, and an ad
8566378 Systems and methods for retry sync mark detection October 22, 2013
Various embodiments of the present invention provide systems and methods for sync mark detection. As an example, a sync mark detection circuit is discussed that includes a storage circuit, a plurality of noise predictive filter circuits, and a controller circuit. The storage circuit
8566281 Method for implementing multi-array consistency groups using a write queuing mechanism October 22, 2013
A method includes applying a write Input/Output (I/O) queue interval to a Logical Unit (LU) member of a consistency group (CG). The method also includes marking each write I/O with a timestamp and suspending I/O from the participating storage array to the LU member of the CG upon the
8565250 Multithreaded, superscalar scheduling in a traffic manager of a network processor October 22, 2013
Described embodiments schedule packets for transmission by a network processor. A traffic manager generates a scheduling hierarchy having a root scheduler and N levels. The network processor generates tasks corresponding to received packets. The traffic manager enqueues tasks in an a
8565048 Unipolar current driver October 22, 2013
Various embodiments of the present invention provide single-ended and differential current drivers for heat assisted magnetic recording and other applications. For example, a current driver is disclosed that includes an upper output terminal and lower output terminal, a number of cur
8565047 Systems and methods for data write loopback based timing control October 22, 2013
Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted loopback circuit is discussed that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The read circuit is operable to
8564897 Systems and methods for enhanced sync mark detection October 22, 2013
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream.
8564337 Clock tree insertion delay independent interface October 22, 2013
Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer c
8302083 Architecture and implementation method of programmable arithmetic controller for cryptographic a October 30, 2012
An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably
8301861 Startup reconstruction of logical-to-physical address translation data for solid state disks October 30, 2012
Described embodiments provide reconstruction of logical-to-physical address mapping data for one or more sectors of a storage device at startup of a media controller. The sectors of the storage device are organized into blocks and superblocks and the address mapping data is stored in
8300684 Real-time eye monitor for statistical filter parameter calibration October 30, 2012
In described embodiments, filter parameters for a filter applied to a signal in, for example, a Serializer/De-serializer (SerDes) receiver and/or transmitter are generated based on real-time monitoring of a data eye. The real-time eye monitor monitors data eye characteristics of the
8300349 Systems and methods for format efficient calibration for servo data based harmonics calculation October 30, 2012
Various embodiments of the present invention provide systems and methods for servo data based harmonics calculation. For example, a method for calculating harmonics is disclosed that includes: providing a data processing circuit; receiving a first data set derived from a data source

 
 
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