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Kabushiki Kaisha Toshiba Patents
Assignee:
Kabushiki Kaisha Toshiba
Address:
Tokyo, JP
No. of patents:
34015
Patents:












Patent Number Title Of Patent Date Issued
RE43779 Image forming apparatus October 30, 2012
An operation device displays, in a display unit, an input screen to input setting information on an insertion sheet designated by a user, and sets the insertion sheet based on contents input in the input screen of an insertion sheet setting displayed in the display unit, in a case where
RE43763 Image forming apparatus October 23, 2012
An operation device displays, in a display unit, an input screen to input setting information on an insertion sheet designated by a user, and sets the insertion sheet based on contents input in the input screen of an insertion sheet setting displayed in the display unit, in a case where
RE43749 MRI system and MR imaging method October 16, 2012
An ECG-prep scan is used to set an optimum time phase in both systole and diastole of the heart. At each of the different time phases, an imaging scan is started to acquire a plurality of sets of echo data. An artery/vein visually separated blood flow image is produced from the echo
RE43713 Base station for a radio communication with a radio terminal and method October 2, 2012
A large amount of user information is transmitted with good efficiency by means of a high-speed downlink by making transmission rates of an uplink circuit and a downlink asymmetrical. The radio communication system includes a plurality of base stations, a plurality of terminals, an u
RE43659 Method for making a design layout of a semiconductor integrated circuit September 11, 2012
A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for
RE43654 Base station for a radio communication with a radio terminal September 11, 2012
A large amount of user information is transmitted with good efficiency by means of a high-speed downlink by making transmission rates of an uplink circuit and a downlink asymmetrical. The radio communication system includes a plurality of base stations, a plurality of terminals, an u
RE43637 Magnetic resonance imaging using preparation scan for optimizing pulse sequence September 11, 2012
To optimize in advance a desired image quality determining pulse sequence parameter incorporated in an imaging scan, a preparation scan is adopted. The preparation scan is performed with the amount of at least one desired image quality parameter changed for each of plural preparatory ima
RE43524 Wireless communication system and wireless station July 17, 2012
A station determines the presence/absence of directional beam control in an access point, on the basis of received power measured when data transmitted from the access point are received, and the type of the received data. In accordance with the result of this determination, the stat
RE43521 Method for manufacturing semiconductor device, including multiple heat treatment July 17, 2012
A semiconductor device manufacturing method having forming first and second insulating gate portions spaced from each other on a semiconductor substrate, selectively implanting the first conductivity type impurity ions to the first gate electrode and a surface layer of the semiconductor
RE43448 Multifunction peripheral with template registration and template registration method June 5, 2012
In a display unit, a setting check key for checking present set contents is displayed together with a setting screen such as a basic screen for performing various basic settings. In a case where a user indicates a setting check key displayed in the setting screen, the display unit di
RE43320 Semiconductor device and manufacturing method thereof April 24, 2012
There is disclosed a semiconductor device comprising a first metal wiring buried in a first wiring groove formed, via a first barrier metal, in a first insulating layer formed on a semiconductor substrate, a second insulating layer formed on the first metal wiring, a via plug formed of a
RE43272 X-ray computerized tomographic apparatus March 27, 2012
An X-ray computerized tomographic apparatus includes an X-ray tube device configured to irradiate an object to be examined with a pyramidal X-ray beam, a detector which has a plurality of detecting elements arrayed in a slice direction in which X-rays transmitted through the object are
RE43229 Method for manufacturing semiconductor device, including multiple heat treatment March 6, 2012
A semiconductor device manufacturing method having forming first and second insulating gate portions spaced from each other on a semiconductor substrate, selectively implanting the first conductivity type impurity ions to the first gate electrode and a surface layer of the semiconductor
RE43159 Semiconductor light emitting device February 7, 2012
A semiconductor light emitting device includes a hetero-configuration having an active layer, a first clad layer, and a second clad layer, the active layer being interposed between the clad layers. The active layer emits light when charge carriers are injected. The first and second clad
RE42742 Image inputting apparatus and image forming apparatus using four-line CCD sensor September 27, 2011
A four-line CCD sensor is structured by line sensors R, G, B in which color filters are respectively disposed on surfaces of light receiving elements, and a line sensor BK at which no color filter is disposed. Amplitudes of signals which are outputted from the line sensors R, G, B at
RE42621 Moving-picture signal coding and/or decoding system resistant to transmission error August 16, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42591 Moving-picture signal coding and/or decoding system resistant to transmission error August 2, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42571 Moving-picture signal coding and/or decoding system resistant to transmission error July 26, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42520 Moving-picture signal coding and/or decoding system resistant to transmission error July 5, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42519 Moving-picture signal coding and/or decoding system resistant to transmission error July 5, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42518 Moving-picture signal coding and/or decoding system resistant to transmission error July 5, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42505 Moving-picture signal coding and/or decoding system resistant to transmission error June 28, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42504 Moving-picture signal coding and/or decoding system resistant to transmission error June 28, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42503 Moving-picture signal coding and/or decoding system resistant to transmission error June 28, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42502 Moving-picture signal coding and/or decoding system resistant to transmission error June 28, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42501 Moving-picture signal coding and/or decoding system resistant to transmission error June 28, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42500 Moving-picture signal coding and/or decoding system resistant to transmission error June 28, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42474 Moving-picture signal coding and/or decoding system resistant to transmission error June 21, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42456 Moving-picture signal coding and/or decoding system resistant to transmission error June 14, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42455 Moving-picture signal coding and/or decoding system resistant to transmission error June 14, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42454 Moving-picture signal coding and/or decoding system resistant to transmission error June 14, 2011
An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the addi
RE42398 Memory system May 24, 2011
In a memory system using a removable recording medium and data stored in the recording medium, identifying information for identifying each recording medium from others is held in the recording medium, and when data stored in the recording medium is used, the identifying information
RE42302 Method for making a design layout and mask April 19, 2011
A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for
RE42294 Semiconductor integrated circuit designing method and system using a design rule modification April 12, 2011
A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for
RE42290 Document scanning apparatus and document scanning method for sequentially scanning documents and April 12, 2011
A first scan unit sequentially transports and scans documents from a document tray, and a second scan unit scans a document placed on a glass plane. A first select unit selects the first or second scan unit according to a predetermined rule when a start instruction is accepted. An ac
RE42180 Semiconductor device having metal silicide layer on source/drain region and gate electrode and m March 1, 2011
A semiconductor device includes a semiconductor substrate, an element-isolating region formed in the semiconductor substrate, a real element region formed in the semiconductor substrate and outside the element-isolating region and having a metal silicide layer formed on the surface t
RE42158 Semiconductor device and manufacturing method thereof February 22, 2011
A semiconductor device is comprised of a semiconductor element having a low dielectric constant insulating film, first electrode pads and barrier metal layers; and a substrate having second electrode pads corresponding to the first electrode pads. The first electrode pads and the second
RE42120 Multi-state EEPROM having write-verify control circuit February 8, 2011
An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plural
RE42081 Information transmission apparatus, traffic control apparatus, method of managing bandwidth reso January 25, 2011
A notification parameter file, which time-sequentially shows a characteristic of the transmission rate change corresponding to the durable time of a traffic, is notified to a network from a server comprising a storage medium storing data having a traffic characteristic ensured at a t
RE41975 Interconnector line of thin film, sputter target for forming the wiring film and electronic comp November 30, 2010
An interconnector line of thin film comprising 0.001 to 30 at % of at least one kind of a first element capable of constituting an intermetallic compound of aluminum and/or having a higher standard electrode potential than aluminum, for example, at least one kind of the first element
RE41969 Multi-state EEPROM having write-verify control circuit November 30, 2010
An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plural
RE41950 Multi-state EEPROM having write-verify control circuit November 23, 2010
An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plural
RE41948 Semiconductor device having multi-layered wiring November 23, 2010
A semiconductor device is provided with a first insulating film, a first wiring layer formed in the first insulating film, a second insulating film formed above the first wiring layer and the first insulating film, the second insulating film including a low dielectric constant film, a
RE41838 Output buffer circuit and semiconductor memory using the same October 19, 2010
An output buffer circuit of the present invention includes a plurality of unit circuits in each of which a pull-up transistor controlled by a first input signal is connected between a high-potential power supply and common node, and a pull-down transistor controlled by a second input
RE41772 Router device and datagram transfer method for data communication network system September 28, 2010
A router device realizing a datagram transfer method for improving the datagram transfer efficiency by ascertaining the transfer target and/or the requested quality of service without referring to the datagram content. The router device has network interfaces connected with networks
RE41742 Optoelectronic conversion header, LSI package with interface module, method of manufacturing opt September 21, 2010
In an optoelectronic conversion header, a ferrule holds an optical waveguide in a predetermined position so that an end face of the optical waveguide protrudes from an mounting surface of the ferrule. An electric wire is provided on the mounting surface of the ferrule, a optical semi
RE41485 Multi-state EEPROM having write-verify control circuit August 10, 2010
An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plural
RE41468 Multi-state EEPROM having write-verify control circuit August 3, 2010
An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plural
RE41456 Multi-state EEPROM having write-verify control circuit July 27, 2010
An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plural
RE41244 Multi-state EEPROM having write-verify control circuit April 20, 2010
An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plural

 
 
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