| Patent Number |
Title Of Patent |
Date Issued |
| 7426214 |
Multiple level minimum logic network |
September 16, 2008 |
| A network or interconnect structure 100 utilizes a data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Switching control is distributed throughout multiple nodes 102 in the structure so that a supervisory controller |
| 7397799 |
Highly parallel switching systems utilizing error correction |
July 8, 2008 |
| An interconnect structure comprises a logic capable of error detection and/or error correction. A logic formats a data stream into a plurality of fixed-size segments. The individual segments include a header containing at least a set presence bit and a target address, a payload conta |
| 7382775 |
Multiple-path wormhole interconnect |
June 3, 2008 |
| A family of interconnect structures, switches that exploit the interconnect structures to attain scalability, low latency, and single-chip implementations. The disclosed interconnect structures and switches support a wide variety of applications including supercomputer interconnects, |
| 7221677 |
Scalable apparatus and method for increasing throughput in multiple level minimum logic networks |
May 22, 2007 |
| A network or interconnect structure which includes a plurality of nodes which are interconnected within a hierarchical multiple level structure. The level of each node is determined by the position of the node within the structure and data messages move from node to node from a source |
| 7205881 |
Highly parallel switching systems utilizing error correction II |
April 17, 2007 |
| An interconnection network has a first stage network and a second stage network and a collection of devices outside the network so that a first device is capable of sending data to a second device. The first stage network is connected to inputs of the second stage network. The first and |
| 7016363 |
Scaleable interconnect structure utilizing quality-of-service handling |
March 21, 2006 |
| An interconnect structure and method of communicating messages on the interconnect structure assists high priority messages to travel through the interconnect structure at a faster rate than normal or low priority messages. An interconnect structure includes a plurality of nodes with a |
| 6754207 |
Multiple-path wormhole interconnect |
June 22, 2004 |
| A family of interconnect structures, switches that exploit the interconnect structures to attain scalability, low latency, and single-chip implementations. The disclosed interconnect structures and switches support a wide variety of applications including supercomputer interconnects, |
| 6289021 |
Scaleable low-latency switch for usage in an interconnect structure |
September 11, 2001 |
| A scalable low-latency switch extends the functionality of a multiple level minimum logic interconnect structure for usage in computers of all types, networks and communication systems. The multiple level minimum logic interconnect structure employs a data flow technique based on timing |
