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Integrated Memory Technologies, Inc. Patents
Assignee:
Integrated Memory Technologies, Inc.
Address:
Santa Clara, CA
No. of patents:
20
Patents:












Patent Number Title Of Patent Date Issued
7407857 Method of making a scalable flash EEPROM memory cell with notched floating gate and graded sourc August 5, 2008
An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source
7199424 Scalable flash EEPROM memory cell with notched floating gate and graded source region April 3, 2007
An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source
7009244 Scalable flash EEPROM memory cell with notched floating gate and graded source region March 7, 2006
An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source
6967870 Combination NAND-NOR memory device November 22, 2005
An integrated circuit memory device has an array of non-floating gate non-volatile flash cells arranged in a NOR configuration. The device further has page buffers and control circuits to operate the array in either a NAND mode of operation or a NOR mode of operation. Finally, the ar
6764905 Method of manufacturing a scalable flash EEPROM memory cell with floating gate spacer wrapped by July 20, 2004
A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion o
6621115 Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate September 16, 2003
A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion o
6614715 Integrated circuit memory device having interleaved read and program capabilities and methods of September 2, 2003
A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to
6556508 Integrated circuit memory device having interleaved read and program capabilities and methods of April 29, 2003
A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to
6507514 Integrated circuit memory chip for use in single or multi-chip packaging January 14, 2003
An integrated circuit chip suitable for use in either a single chip packaged configuration or a multi-chip packaged configuration is disclosed. The chip has a conventional memory circuit portion and a control circuit portion. In operation as a single chip packaged configuration, the
6496415 Non-volatile memory device having high speed page mode operation December 17, 2002
A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, a plurality of page latches 18L, and a plurality of Quick Current Level Translators (QCLT). Each QCLT
6469955 Integrated circuit memory device having interleaved read and program capabilities and methods of October 22, 2002
A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to
6377507 Non-volatile memory device having high speed page mode operation April 23, 2002
A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, a plurality of page latches 18L, and a plurality of Quick Current Level Translators (QCLT). Each QCLT
6259625 Method and apparatus for reducing high current chip erase in flash memories July 10, 2001
A method and an apparatus is provided to decrease the erase current level by subdividing the memory array into small segments and cycle through complete address space sequentially during the chip erase operation. Therefore, the transient erase current is proportionally reduced and is
6232185 Method of making a floating gate memory cell May 15, 2001
A method for making a non-volatile memory cell having a select gate, a floating gate and a control gate of the completely self-aligned type, partially self-aligned type and non-aligned type is disclosed. Further, each of the three types of cells has a floating gate, whose linear dime
6134149 Method and apparatus for reducing high current during chip erase in flash memories October 17, 2000
A method and an apparatus is provided to decrease the erase current level by subdividing the memory array into small segments and cycle through complete address space sequentially during the chip erase operation. Therefore, the transient erase current is proportionally reduced and is
6134144 Flash memory array October 17, 2000
A novel flash memory array has an array of memory cells with each memory cell being of a floating gate memory transistor with a plurality of terminals. The memory cells are arranged in a plurality of rows and a plurality of columns, with a word line connecting the memory cells in the
6057575 Scalable flash EEPROM memory cell, method of manufacturing and operation thereof May 2, 2000
A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first edge and a second edge with a first portion over the select g
5912843 Scalable flash EEPROM memory cell, method of manufacturing and operation thereof June 15, 1999
A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first portion over the select gate and insulated therefrom, and a s
5886887 Voltage multiplier with low threshold voltage sensitivity March 23, 1999
A voltage multiplier has a number of electrically-like stages. Each of the stages receives two input signals and a pump signal. The stage has an MOS transistor with a first source/drain region and a second source/drain region and a gate. Each stage also has means for receiving a pump sig
5856943 Scalable flash EEPROM memory cell and array January 5, 1999
A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first portion over the select gate and insulated therefrom, and a s

 
 
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