| Patent Number |
Title Of Patent |
Date Issued |
| RE39227 |
Content addressable memory (CAM) arrays and cells having low power requirements |
August 8, 2006 |
| A content addressable memory (CAM) cell that includes a static random access memory (SRAM) cell that operates in response to a V.sub.CC supply voltage. A first set of bit lines coupled to the SRAM cell are used to transfer data values to and from the SRAM cell. The signals transmitted |
| RE36907 |
Leadframe with power and ground planes |
October 10, 2000 |
| A leadframe for use in an integrated circuit package is described. The leadframe comprises a plurality of electrically conductive leads, a die attach pad, and an electrically conductive ring or rings formed generally around the circumference of the die attach pad and between the die atta |
| 7622689 |
Switch actuator |
November 24, 2009 |
| A switch activator includes a tongue including a first end and a second end and a surrounding portion. The tongue is joined to the surrounding portion at the first end and has a pressing point adjacent the second end. The tongue may be joined by glue, a heat stake or a rivet. Prefera |
| 7617346 |
Rapid input/output doorbell coalescing to minimize CPU utilization and reduce system interrupt l |
November 10, 2009 |
| Status/error reporting is implemented using a doorbell system. A plurality of flag registers are included on a system device, such as a serial buffer. Each flag register has a corresponding address, and stores a plurality of flags. A flag scan controller accesses the flag registers in |
| 7602318 |
Method and apparatus for improved efficiency in protocols using character coding |
October 13, 2009 |
| A method and apparatus for improved efficiency in protocols using character coding have been disclosed. |
| 7602226 |
Method and apparatus for clock generation |
October 13, 2009 |
| A method and apparatus for clock generation have been disclosed having a selector logic block that controls operation based upon inputs such as analog input(s), digital input(s), a lookup table, and preset value(s), and combinations of such. |
| 7598775 |
Phase and frequency detector with zero static phase error |
October 6, 2009 |
| A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PFD signals. Pulse b |
| 7596142 |
Packet processing in a packet switch with improved output data distribution |
September 29, 2009 |
| A packet switch includes a packet processor for processing data packets. The packet processor receives a data packet including a data payload, identifies data portions in the data payload, and determines a destination address for each data portion. Additionally, the packet processor |
| 7594149 |
In-situ monitor of process and device parameters in integrated circuits |
September 22, 2009 |
| In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention is coupled to a scan path circuit and includes an input circuit coupled to a parameter testing circuit and an output driver coupled |
| 7590025 |
Systems and methods for clean DQS signal generation in source-synchronous DDR2 interface design |
September 15, 2009 |
| A method and circuit for generating a signal to synchronize DQ data transfer in memory interface design is presented. The presented method includes receiving a strobe signal having a preamble period before and post-amble period after data transfer burst synchronization signal edge tr |
| 7589738 |
Cache memory management system and method |
September 15, 2009 |
| A cache memory method and corresponding system for two-dimensional data processing, and in particular, two-dimensional image processing with simultaneous coordinate transformation is disclosed. The method uses a wide and fast primary cache memory (PCM) and a deep secondary cache memo |
| 7586347 |
Clock generator with self-bias bandwidth control |
September 8, 2009 |
| A clock generator includes a phase-lock loop for generating an output clock signal based on a reference clock signal. The phase-lock loop includes a charge pump, a low-pass filter, and a self-bias circuit. The low-pass filter generates a bias voltage and the self-bias circuit generat |
| 7586343 |
Output drive circuit that accommodates variable supply voltages |
September 8, 2009 |
| In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a |
| 7583087 |
In-situ monitor of process and device parameters in integrated circuits |
September 1, 2009 |
| In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embo |
| 7582567 |
Method for forming CMOS device with self-aligned contacts and region formed using salicide proce |
September 1, 2009 |
| A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes |
| 7580355 |
Method of performing weighted round-robin queue scheduling using a dynamic link list and structu |
August 25, 2009 |
| A weighted round-robin scheduler includes a round-robin table that stores a plurality of cycle link lists. Each cycle link list includes a head flow identification (FLID) value identifying a first flow of the cycle link list, and a tail FLID value identifying a last flow of the cycle |
| 7579832 |
Cross-drive impedance measurement circuits for sensing audio loads on CODEC channels |
August 25, 2009 |
| An audio system includes a CODEC audio jack having left and right audio ports and a jack sense circuit. The jack sense circuit includes left and right amplifiers and a cross-drive impedance sensing circuit. This cross-drive impedance sensing circuit, which is electrically coupled to |
| 7573896 |
Method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation |
August 11, 2009 |
| A method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed. |
| 7573303 |
Digitally controlled system on-chip (SOC) clock generator |
August 11, 2009 |
| A clock generator includes a clock circuit and a voltage-controlled oscillator in a phase-locked loop. The clock circuit monitors input clock signals and selects one of the input clock signals based on characteristics of the input clock signals. The voltage-controlled oscillator gene |
| 7571337 |
Integrated circuits and methods with transmit-side data bus deskew |
August 4, 2009 |
| A data output circuit includes a plurality of clocked data output buffers, each of which drives a data output thereof responsive to a clock signal and an adjustable multiphase clock signal generator that generates a plurality of clock signals of different phases and that is operative to |
| 7571267 |
Core clock alignment circuits that utilize clock phase learning operations to achieve accurate c |
August 4, 2009 |
| Core clock alignment circuits include a serial-in parallel-out (SIPO) data processing circuit, which is configured to generate a plurality of lanes of deserialized data in response to a corresponding plurality of lanes of serialized data. The SIPO data processing circuit is further confi |
| 7570115 |
Common mode voltage extraction circuit |
August 4, 2009 |
| Consistent with the present invention, there is provided a circuit for extracting a common mode voltage of an input signal. The device may include an operational amplifier having an output, at least one negative input and at least one positive input, a first transistor, and a second |
| 7567100 |
Input clock detection circuit for powering down a PLL-based system |
July 28, 2009 |
| An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time- |
| 7565597 |
Fast parity scan of memory arrays |
July 21, 2009 |
| A novel method for scanning bit parity in a memory array, and a circuit for implementing it, are disclosed. In a memory array that has one or more rows of memory cells, the method for checking data parity includes storing a plurality of data bits in the memory cells, scanning a row of |
| 7564268 |
Low power logic output buffer |
July 21, 2009 |
| A low power logic output buffer includes first and second logic gates, each having an input and an output. The input of the first logic gate receives a first logic signal, and the input of the second logic gate receives a second logic signal. The buffer includes first, second, third |
| 7560936 |
Method and apparatus for ground bounce and power supply bounce detection |
July 14, 2009 |
| A method and apparatus for ground bounce and power supply bounce detection in devices have been disclosed. In one case one input to a differential amplifier is coupled to a reference voltage and another input to the differential amplifier is coupled to a measurement point and the output |
| 7560800 |
Die seal with reduced noise coupling |
July 14, 2009 |
| A die seal structure for sealing integrated circuit devices formed on a semiconductor substrate. The die seal structure includes a die seal and a junction diode. The die seal only connects to the semiconductor substrate through the junction diode, thereby reducing noise coupling through |
| 7558151 |
Methods and circuits for DDR-2 memory device read data resynchronization |
July 7, 2009 |
| The reliable capture of data from a DDR-2 memory device can be provided using timing signals provided by the DDR-2 memory device in conjunction with enable signals generated there from. The reliable capture of data from the DDR-2 DRAM can be used to extend the data valid window for which |
| 7555668 |
DRAM interface circuits that support fast deskew calibration and methods of operating same |
June 30, 2009 |
| A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provid |
| 7554379 |
High-speed, low-power level shifter for mixed signal-level environments |
June 30, 2009 |
| A level shifter is presented that allows fast switching while requiring low power. In accordance with some embodiments of the invention, the level shifter is a two stage level shifting circuit with p-channel and n-channel transistors biased so as to limit the potential between the so |
| 7548105 |
Method and apparatus for source synchronous testing |
June 16, 2009 |
| A method and apparatus for source synchronous testing have been disclosed. In one case a data signal is delayed and a selectively activated delay is applied to a clock. This allows the clock to be positioned before the data and also after the data. |
| 7545660 |
Method and apparatus for CAM with reduced cross-coupling interference |
June 9, 2009 |
| A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed. |
| 7545188 |
Multiphase clock generator |
June 9, 2009 |
| A clock generator generates multiple clock signals based on an input signal and adjusts the phases of the clock signals relative to a phase of the input signal, based on a control signal. The clock generator includes a phase locked loop that includes a phase shift unit. The phase shift |
| 7544556 |
Process for forming CMOS devices using removable spacers |
June 9, 2009 |
| A process for forming CMOS devices is disclosed in which disposable spacers are used to obtain a structure having improved gap-fill characteristics. First, gate film stacks are formed on the substrate. A shallow implant process is performed so as to form shallow source/drain implant |
| 7536614 |
Built-in-redundancy analysis using RAM |
May 19, 2009 |
| A method for testing memory in an integrated circuit device is disclosed. The method includes executing a test routine in a portion of the memory at a speed sufficient to fully test the memory cells, identifying faulty memory cells in the tested portion of the memory; writing an error ma |
| 7523232 |
Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system |
April 21, 2009 |
| In a multi-queue memory system, a plurality of read count pointers (one for each queue) are stored in a read address file, and used to generate empty flags. A read count pointer associated with a first queue is retrieved from the read address file, and it is determined whether the fi |
| 7522438 |
Method and apparatus for CAM with reduced cross-coupling interference |
April 21, 2009 |
| A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed. |
| 7522395 |
Electrostatic discharge and electrical overstress protection circuit |
April 21, 2009 |
| Electrostatic discharge and electrical overstress protection circuit is disclosed to include a discharging circuit, a detection circuit and a controller. The controller is operable to sense and compare the output voltage from the detection circuit to a reference voltage. The controll |
| 7518844 |
Over-voltage tolerant ESD protection circuit |
April 14, 2009 |
| An ESD protection circuit for over-voltage signal bus is disclosed that includes a diode circuit that is electrically connected to a pseudo power supply circuit. The pseudo power supply circuit includes a pseudo first power supply line coupling to an actual first power supply line having |
| 7518842 |
Circuits and methods that attenuate coupled noise |
April 14, 2009 |
| Systems and methods of chip design and package implementation for attenuating noise in timing circuits, including phase-locked-loops (PLL) and delay-locked-loops (DLL), are disclosed. Embodiments of the present invention attenuate coupled noise, such as the effects of ground current |
| 7508893 |
Integrated circuits and methods with statistics-based input data signal sample timing |
March 24, 2009 |
| An integrated circuit device includes a data input configured to receive a data signal and a clock input configured to receive a clock signal associated with the data signal. The device further includes a sample timing circuit coupled to the clock input and the data input and configu |
| 7505468 |
Method and apparatus for logical identification priority |
March 17, 2009 |
| A method and apparatus for logical identification priority have been disclosed. |
| 7499303 |
Binary and ternary non-volatile CAM |
March 3, 2009 |
| A CAM cell array according to embodiments of the present invention include an array of CAM cells, each of the CAM cells comprising a first cell, the first cell including a non-volatile storage element coupled to at least one first data line and a match line; a match line controller coupl |
| 7486531 |
Low power content addressable memory array (CAM) and method of operating same |
February 3, 2009 |
| A content addressable memory (CAM) system that includes a row of NAND-type CAM cells divided into a plurality of segments. Each segment includes a plurality of series-connected switching transistors, wherein each of the switching transistors is part of a corresponding NAND-type CAM cell. |
| 7478186 |
Interrupt coalescer for DMA channel |
January 13, 2009 |
| A DMA interrupt coalescer processes interrupts received from a DMA channel of a DMA controller by transmitting an interrupt request to an interrupt controller if a coalescing condition is satisfied after receiving one or more delayable interrupts, or transmitting the interrupt request |
| 7472322 |
On-chip interface trap characterization and monitoring |
December 30, 2008 |
| A method and apparatus for testing semiconductor wafers is disclosed in which a test circuit is used that includes a waveform generator. The test circuit can test a single transistor or can test multiple transistors. A testing method is disclosed in which a supply voltage is applied to t |
| 7454554 |
Binary base address search device and method |
November 18, 2008 |
| A base address matching device and method are disclosed. In a switching device having a plurality of input/output ports, a routing device has been described that has an array of registers in which each register holds content associating an address with one of the input/output ports i |
| 7447812 |
Multi-queue FIFO memory devices that support flow-through of write and read counter updates usin |
November 4, 2008 |
| Multi-queue first-in first-out (FIFO) memory devices include multi-port register files that provide write count and read count flow-through when the write and read queues are equivalent. According to some of these embodiments, a multi-queue FIFO memory device includes a write flag co |
| 7443747 |
Memory array bit line coupling capacitor cancellation |
October 28, 2008 |
| Capacitive coupling correction circuits are coupled between adjacent parallel dynamic (pre-charged) or static conductors. The capacitive coupling correction circuits effectively isolate a low voltage applied to a first conductor from a high pre-charged voltage stored on an adjacent s |
| 7436224 |
Low variation voltage output differential for differential drivers |
October 14, 2008 |
| The methods and systems presented herein provide an improved means of correcting the variation of Voltage Output Differential (VOD) in differential drivers. In some embodiments, a high-precision reference voltage is generated not only based on a desired VOD, but also by monitoring th |
