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Integrated Device Technology, Inc. Patents
Assignee:
Integrated Device Technology, Inc.
Address:
San Jose, CA
No. of patents:
793
Patents:


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Patent Number Title Of Patent Date Issued
RE39227 Content addressable memory (CAM) arrays and cells having low power requirements August 8, 2006
A content addressable memory (CAM) cell that includes a static random access memory (SRAM) cell that operates in response to a V.sub.CC supply voltage. A first set of bit lines coupled to the SRAM cell are used to transfer data values to and from the SRAM cell. The signals transmitted
RE36907 Leadframe with power and ground planes October 10, 2000
A leadframe for use in an integrated circuit package is described. The leadframe comprises a plurality of electrically conductive leads, a die attach pad, and an electrically conductive ring or rings formed generally around the circumference of the die attach pad and between the die atta
8575981 MEMS-based frequency synthesizers with enhanced temperature compensation November 5, 2013
A frequency synthesizer is configured to generate a periodic output signal in response to a periodic input signal and a temperature-dependent frequency adjusting control signal. A temperature sensor is provided, which is configured to generate a temperature measurement signal in resp
8575819 Microelectromechanical resonators with passive frequency tuning using built-in piezoelectric-bas November 5, 2013
Microelectromechanical resonators include a resonator body with a built-in piezoelectric-based varactor diode. This built-in varactor diode supports passive frequency tuning by enabling low-power manipulation of the stiffness of a piezoelectric layer, in response to controlling charge
8572151 Methods and apparatuses for cordic processing October 29, 2013
A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of
8571050 Method and apparatus to optimize class of service under multiple VCs with mixed reliable transfe October 29, 2013
A method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer (RT) and continuous transfer (CT) modes have been disclosed where outstanding packets to be processed is through a Retransmission Mapper with a VOQ read pointer realignment that can qu
8295293 Predictive flow control for a packet switch October 23, 2012
A packet switch issues credits to a link partner based on credit values and updates the credit values to indicate credits consumed by the link partner based on packets received from the link partner by the ingress port. Additionally, the packet switch selects credit threshold values
8294249 Lead frame package October 23, 2012
A lead frame package is disclosed where transmission signals are coupled into a die from a pair of lead frames through bonding wires that are separated by no more than three times a diameter of one of the bonding wires. In some embodiments, pairs of lead frames carrying differential
8289989 System and method for arbitration using availability signals October 16, 2012
A packet switch includes an arbiter that generates an availability signal indicating whether one or more pseudo-ports are available for receiving data. Each pseudo-port identifies one or more output ports of the packet switch. An input port of the packet switch receives data of a data
8289061 Technique to reduce clock recovery amplitude modulation in high-speed serial transceiver October 16, 2012
A method is provided for improving clock recovery signal jitter in digital communication based on a phase adjustment technique in a phase interpolation. A clock signal is expressed as the combination of two sinusoidal signals. The phase interpolating process determines the amplitude
8285884 Data aggregation system and method for deskewing data at selectable data rates October 9, 2012
A deskew module of a receiver includes deskew units, each of which includes a data aggregation module for selecting a data rate for receiving symbols of a corresponding data stream. The deskew unit includes a data aggregation module that aggregates a predetermined number of the symbo
8284816 Push-pull spread spectrum clock signal generator October 9, 2012
A spread spectrum clock signal generator modulates a reference clock signal based on a spread spectrum frequency profile and includes a phase-lock loop for generating a spread spectrum clock signal by aligning a phase of the modulated reference clock signal with a phase of the spread
8284790 Packet switch with enqueue structure for odering packets October 9, 2012
A packet switch receives packets at an ingress port, generates enqueue records for the packets, and stores the enqueue records in an enqueue structure. The enqueue record of a packet includes a pass flag for indicating whether a permissive passing rule is applicable to the packet. Th
8284091 Flash analog-to-digital converter October 9, 2012
An analog-to-digital converter comprises a signal input (6) for receiving an analog input signal and a set of comparators (4). Each comparator (4) has a first input (21) connected to the signal input (6) and a second input (22) connected to a reference voltage (16). Each comparator g
8283256 Methods of forming microdevice substrates using double-sided alignment techniques October 9, 2012
Methods of forming substrates having two-sided microstructures therein include selectively etching a first surface of the substrate to define a plurality of alignment keys therein that extend through the substrate to a second surface thereof. A direct photolithographic alignment step is
8279007 Switch for use in a programmable gain amplifier October 2, 2012
A switch circuit is provided. The switch circuit may include a first transistor having a source terminal to accept an input signal, a drain terminal to provide an output signal, and a gate; a power supply providing a gate voltage. The switch circuit may also include a circuit to coup
8265219 Method and apparatus for fast PLL initialization September 11, 2012
A method and apparatus for fast PLL initialization have been disclosed where control of a VCO is based on a selected control signal which is based upon either a comparison signal or a prespecified signal.
8259888 Method of processing signal data with corrected clock phase offset September 4, 2012
The present invention provides a method of processing signal data comprising generating a first clock signal and a second clock signal and processing the signal data using the first clock signal and the second clock signal. While processing the signal data, the phase difference betwe
8255599 Packets transfer device having data absorbing buffers with elastic buffer capacities August 28, 2012
In PCI-Express and alike communications systems, data bandwidth per channel can vary as a result of negotiated port bifurcation during network bring-up. Disclosed are systems and methods for adjusting FIFO depths in response to negotiated bandwidth per channel so that data absorbing
8254515 Method for measuring phase locked loop bandwidth parameters for high-speed serial links August 28, 2012
A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator; determining a reference jitter amplitude
8254399 Method and apparatus for adaptive buffer management for traffic optimization on switches August 28, 2012
A method and apparatus for adaptive buffer management for traffic optimization on switches have been disclosed where pattern injection and traffic monitoring with forced congestion allows optimizing buffers while accounting for actual system delays.
8248741 Apparatuses and methods for a SCR-based clamped electrostatic discharge protection device August 21, 2012
A SCR-based based electrostatic discharge protection device with a shunt path is provided. The shunt path operates at a low resistance when an enabling signal of the shunt path is asserted and a high resistance when the enabling signal is negated. The shunt path connects the cathode and
8248383 Multi-touch touch screen with single-layer ITO bars arranged in parallel August 21, 2012
A touch screen includes a plurality of single-layer ITO bars having a substantially rectangular shape and arranged in parallel to each other in order to detect touches on the touch screen. The location of a touch on the touch screen in the direction along an ITO bar is determined by
8248135 Circuit including current-mode logic driver with multi-rate programmable pre-emphasis delay elem August 21, 2012
A circuit (10) includes a circuit input (12), a circuit output (16) and a one or more delay elements (22) positioned between the circuit input (12) and the circuit output (16). The delay elements (22) each include a differential input pair (234), a latch stage (236) and a delay controlle
8238577 Audio system with tone controller for use in a computer August 7, 2012
A computer audio system includes an audio codec and a lone controller. The audio codec is operably coupled to receive audio information, which includes tone control settings, PCM digital audio inputs and PCM digital audio outputs. In addition, the audio codec may receive audio informatio
8238339 Method and apparatus for selective packet discard August 7, 2012
A method and apparatus for selective packet discard have been disclosed where two bits are added to a packet to indicate various discard options.
8237624 System having capability for daisy-chained serial distribution of video display data August 7, 2012
A serial display interface such as the VESA-Display Port interface is expanded to support daisy chained coupling of one display monitor to the next. Each daisy chain wise connectable display monitor has a local daisy chain transceiver device associated with it where the local transceiver
8234424 Efficient strip-down and re-alignment of ingressing physical layer/data layer packets in an aggr July 31, 2012
In PCI-Express and alike communications systems, number of lanes used per channel or port can vary as a result of negotiated lane aggregation during network bring-up. Disclosed are systems and methods for efficiently realigning packet data and stripping out control bytes in a by-eigh
8233639 Audio codec producing a tone controlled output July 31, 2012
An audio codec includes an input for receiving audio information. Audio processing circuitry produces a first stereo audio signal, a second stereo audio signal, and a monotone audio signal based on the audio information. A low pass filter filters the monotone audio output, wherein th
8230174 Multi-queue address generator for start and end addresses in a multi-queue first-in first-out me July 24, 2012
A multi-queue FIFO memory device that uses existing pins of the device to load a desired number of queues (N) into a queue number register is provided. The queue number register is coupled to a queue size look-up table (LUT), which provides a queue size value in response to the conte
8217689 Method and circuit for DisplayPort video clock recovery July 10, 2012
A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is d
8213448 Method to support lossless real time data sampling and processing on rapid I/O end-point July 3, 2012
A serial buffer monitors an incoming stream of packets to identify single missing packets and multiple consecutive missing packets. Upon detecting multiple consecutive missing packets, an interrupt is generated, thereby stopping the data transfer. Upon detecting a single missing packet,
8212594 Methods and apparatuses for clock domain crossing July 3, 2012
Clock-domain-crossing systems and methods include an integrator that accumulates input samples over multiple clock cycles in a first clock domain to generate an accumulation result. Clock-domain-crossing circuitry samples the accumulation result in the first clock domain after each o
8199042 Apparatuses and methods for physical layouts of analog-to-digital converters June 12, 2012
Physical layouts of integrated circuits are provided, which may include an analog-to-digital converter including a plurality of comparators. Individual transistors of each comparator of the plurality are arranged in a one-dimensional row in a first direction. Neighboring comparators of
8194721 Signal amplitude distortion within an integrated circuit June 5, 2012
An integrated circuit 2 includes a serial data transmitter 12 and a serial data receiver 14. A signal amplitude distorting circuit 30 is provided to introduce distortion in the amplitude of a serial data signal generated by the serial data transmitter 12 and looped back to the serial
8179952 Programmable duty cycle distortion generation circuit May 15, 2012
An integrated circuit is provided comprising: a serial transmitter, a serial receiver and a serial connection providing communication between the serial transmitter and the serial receiver. The integrated circuit further comprises a duty cycle distortion circuit so that the integrated
8179372 Electronic display with array context-sensitive search (ACS) technology May 15, 2012
A system and method for efficient computation in the course of locating a position on the face of a touch-screen-equipped display device by limiting the amount of computations to weighted vectors within a range substantially less than the entire range of data input from the touch scr
8174969 Congestion management for a packet switch May 8, 2012
A packet switch includes a flow control circuit for preventing a downstream ingress port of the packet switch from providing a non-posted packet to an upstream egress port of the packet switch when a downstream egress port of the packet switch is congested. As a result, congestion is
8174428 Compression of signals in base transceiver systems May 8, 2012
A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses signal samples resulting from
8164367 Spread spectrum clock generation technique for imaging applications April 24, 2012
A clock signal generator includes a phase-lock loop for generating an imaging clock signal having a frequency based on a reference clock signal. The imaging clock signal generator also includes a modulation circuit for determining a number of pixels in a horizontal line of an image t
8161210 Multi-queue system and method for deskewing symbols in data streams April 17, 2012
A communication system includes a transmitter that transmits multiple data streams to a receiver in the communication system. Each of the data streams includes data and a skip ordered set. The receiver includes a deskew unit for each data stream, each of which includes multiple data
8160272 Audio output circuits having ramped attenuation circuits that inhibit pop disturbances when audi April 17, 2012
An audio output circuit includes a port attenuation circuit, which is configured to convert an abrupt dc voltage offset transition between a pair of audio signals received in sequence at an input thereof into a more gradual transition. This conversion is achieved by performing, in se
8154880 Method and apparatus for active line interface isolation April 10, 2012
A method and apparatus for active line interface isolation have been described.
8151132 Memory register having an integrated delay-locked loop April 3, 2012
A memory device is provided. The memory device includes a plurality of memory chips coupled in series, and a register serially coupled to the memory chips. The register includes an integrated delay-locked loop. The memory device may be included in a processing system. Moreover, a method
8149553 Electrostatic discharge event protection for an integrated circuit April 3, 2012
An integrated circuit 2 is provided with a clamp transistor 20 for providing electrostatic discharge event protection. A detector circuit 28 produces a clamp control signal for switching the clamp transistor 20 to a conductive state so as to provide the electrostatic discharge protec
8149224 Computing system with detachable touch screen device April 3, 2012
A computing system includes a computer device and a detachable touch screen device. The computer device receives input from a touch screen of a detachable touch screen device when the detachable touch screen device is attached to a touch screen port of the computer device and displays an
8138845 Method and apparatus for auto-frequency calibration for multi-band VCO March 20, 2012
A method and apparatus for auto-frequency calibration for multi-band VCO have been disclosed where a VCO is first adjusted to a major frequency band and then adjusted to a sub-band within the major frequency band.
8134414 Clock, frequency reference, and other reference signal generator with frequency stability over t March 13, 2012
Exemplary embodiments provide a reference signal generator having a reference or center frequency within a predetermined variance over variations in temperature within a specified range. An exemplary apparatus comprises a reference resonator to generate a first reference signal havin
8129964 Interleaved/all-phase mode switched PWM system March 6, 2012
A multi-phase power switching converter having first and second states includes a pulse width modulator having an output, a converter output providing an output signal, and a plurality of drivers, each having an output electrically coupled to the converter output and an input. When t
8127187 Method and apparatus of ATE IC scan test using FPGA-based system February 28, 2012
An apparatus and a method for enhancing the use of automated test equipment (ATE), are presented. The apparatus comprises a test load board that mounts a plurality of devices to be tested (DUTs), and a daughter card communicating with the test board and the ATE, testing each of the p
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