| Patent Number |
Title Of Patent |
Date Issued |
| RE40352 |
Switch mode power supply with reduced switching losses |
June 3, 2008 |
| The invention relates to a switching transistor presenting reduced switching losses. In the switching transistor, output capacitance is very high when drain/source voltages are low. As the drain/source voltage increases, the capacitance falls to such low values that the energy stored |
| RE40292 |
Bandpass filter |
May 6, 2008 |
| The bandpass filter has a comparatively large pass bandwidth, with, at the same time, comparatively steep edges up to the stop band and low attenuation in the passband. The bandpass filter contains three parallel LC elements, one of which is connected between the bandpass filter input |
| RE40275 |
Method for producing a memory cell |
April 29, 2008 |
| A method for producing a memory cell includes masking a desired polysilicon structure with an oxidation-inhibiting layer, preferably a nitride layer. The polysilicon above source/drain regions and field regions is then converted into silicon dioxide. At the same time, filling with si |
| RE39799 |
Memory cell array and method for manufacturing it |
August 28, 2007 |
| In a storage cell array, a first and a second line are provided which have a crossing point, at which a storage element with magnetoresistive effect is disposed. A yoke is provided which surrounds one of the lines and that contains magnetizable material with a permeability of at least 10 |
| RE39283 |
Method for selective filtering |
September 12, 2006 |
| A method for digital clock recovery and selective filtering includes prescribing or calculating first coefficients of a prototype of a selective filter at a characteristic frequency fc for a given sampling frequency fa. Second coefficients of a selective filter are calculated at the |
| RE39124 |
Integrated circuit having capacitive elements |
June 13, 2006 |
| An integrated circuit having capacitive elements for smoothing a supply voltage is described. In this case, at least one additional metal electrode, which is configured as a high frequency-optimized capacitance and is distinguished by an extremely low sheet resistance, is connected i |
| RE38280 |
Optoelectronic module for bidirectional optical data transmission |
October 21, 2003 |
| An optoelectric module for bidirectional optical data transmission has a molded element provided as a beam splitter, which consists essentially of a material that is transparent for the emitted radiation and the received radiation, and in which a beam splitter is embedded. A transmitting |
| RE38184 |
Circuit for displaying operating states of a device |
July 15, 2003 |
| A circuit receives at least two input signals and produces exactly three output signals in response to the two input signals, whereby two of the output signals shine constantly in an activated state and the third output signal shines constantly or flashes in the activated state. Each tim |
| RE37930 |
DRAM including an address space divided into individual blocks having memory cells activated by |
December 10, 2002 |
| A DRAM with an address space divided into blocks, in which storage cells of individual blocks can be activated by a row address signal (RAS) furnished by a controller. Each individual block can then be activated by an independent activation signal derived from the row address signal. The |
| D474473 |
Multimedia chip card |
May 13, 2003 |
|
| D446769 |
Process plug |
August 21, 2001 |
|
| 7620884 |
Memory checking device and method for checking a memory |
November 17, 2009 |
| A memory checking device for cells arranged in memory rows and columns, wherein, in a state of integrity, the memory has parity values for two memory rows or two columns that differ from each other with the same parity value calculation rule or with different parity value calculation |
| 7620857 |
Controllable delay device |
November 17, 2009 |
| Two delay chains having in each case n series-connected unidirectional delay elements are provided for controllably delaying electrical signals between a circuit input and at least one circuit output. Each delay element is an active circuit with a fixed transit time. The input of the |
| 7620835 |
Voltage supply control device and method |
November 17, 2009 |
| One embodiment of the invention provides a voltage supply control device, as well as a process for the control of the voltage supply of a semiconductor component, which can be operated in at least two different voltage supply modes. The process includes detecting the level of a volta |
| 7620745 |
Transferring data between a memory and peripheral units employing direct memory access control |
November 17, 2009 |
| A method transfers data between a memory and peripheral units. The method includes assigning priorities to the data to be transferred, and transferring the data by direct memory access (DMA) control between the memory and the peripheral units in conformity with the priorities assigne |
| 7620136 |
Clock and data recovery circuit having gain control |
November 17, 2009 |
| A clock and data recovery circuit includes a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal, a gain stage configured to apply a gain to the phase error signal to provide an amplified phase error signal, and a |
| 7620100 |
Method and apparatus for equalization of a signal which is transmitted via a user channel using |
November 17, 2009 |
| In a method for equalization of a signal that is transmitted via a user channel using the DF method, an interference channel is taken into account by the DF contribution that is used for processing of the user channel trellis diagram containing information about the interference chan |
| 7619980 |
System operable to transmit and receive messages |
November 17, 2009 |
| A system, minimising transmission delays and avoiding loss of synchronisation, using a contention based multiple access protocol comprises n transceivers each comprising a detector for detecting the condition of the medium and connected to a controller for switching the transceiver f |
| 7619487 |
Polar modulation without analog filtering |
November 17, 2009 |
| This disclosure relates to systems and methods for polar modulation without analog filters. Digitals filters, a second order hold interpolator and a reconfigurable third order noise shaper can be used instead of the analog filters used in conventional polar modulators. The polar modu |
| 7619310 |
Semiconductor interconnect and method of making same |
November 17, 2009 |
| An integrated circuit interconnect structure includes a conductive line, a first barrier layer disposed on a bottom surface of conductive line, a second barrier layer disposed on the top surface of the conductive line, and an interlevel dielectric surrounding the conductive line. |
| 7619309 |
Integrated connection arrangements |
November 17, 2009 |
| A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive |
| 7619304 |
Panel and semiconductor component having a composite board with semiconductor chips and plastic |
November 17, 2009 |
| A panel and a semiconductor component including a composite board with semiconductor chips and plastic package molding compound and a method for the production thereof is disclosed. In one embodiment, the panel includes a composite board with semiconductor chips arranged in rows and |
| 7618867 |
Method of forming a doped portion of a semiconductor and method of forming a transistor |
November 17, 2009 |
| A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer |
| 7618865 |
Method in the fabrication of a monolithically integrated vertical device on an SOI substrate |
November 17, 2009 |
| A method in the fabrication of a monolithically integrated vertical device on an SOI substrate comprises the steps of providing an SOI substrate including, from bottom to top, a silicon bulk material, an insulating layer, and an monocrystalline silicon layer; forming an opening in the |
| 7618845 |
Fabrication of an integrated circuit package |
November 17, 2009 |
| A QFN integrated circuit is mounted on a leadframe having multiple lead lands and resin material encapsulates the integrated circuit leaving the lead lands exposed. Subsequently a sawing operation divides the lead lands into multiple leads, and the leadframe and resin material are pa |
| 7618492 |
Methods of forming nanocrystals |
November 17, 2009 |
| Methods of selectively forming nanocrystals on semiconductor devices are disclosed. Regions of a workpiece are masked with a masking material, and the nanocrystals are formed on the unmasked regions. The nanocrystals may be formed by exposing the masked workpiece to a first substance, an |
| 7617067 |
Multichip package with clock frequency adjustment |
November 10, 2009 |
| One embodiment of the present invention provides a multi-chip package including a logic device providing a clock signal having a frequency and a memory device. The memory device receives the clock signal and operates at the clock signal frequency. The memory device includes a temperature |
| 7616714 |
Process and device for the prediction of noise contained in a received signal |
November 10, 2009 |
| A device and method for predicting noise in a signal that is received by a digital receiver is provided. The device includes an autocorrelation function determination device and a noise predictor device. Also included in the device is an adaptive filter that produces a prediction error |
| 7616680 |
Method for processing data in a spread spectrum system |
November 10, 2009 |
| A method for processing data in a spread spectrum system, including decimating a data rate of received spread spectrum data by a decimation factor to a decimated rate; storing the received spread spectrum data into a memory at the decimated rate; interpolating the decimated rate by a |
| 7616662 |
Parser for parsing data packets |
November 10, 2009 |
| A parser system is arranged to receive a data stream (1) having interleaved sections derived from a plurality of different packets, and to extract data from each section as it arrives. The parser system has a scanning section which receives information about each of the sections of d |
| 7616059 |
Temperature compensation of small signal gain of an amplifier stage |
November 10, 2009 |
| The invention relates to an differential amplifier circuit comprising an amplifier stage comprising a first and a second transistor, the gates of which are connected to differential input terminals of the amplifier stage. The differential amplifier further comprises a temperature com |
| 7615852 |
Semiconductor component in a housing with mechanically inforcing flat conductor webs |
November 10, 2009 |
| The standard housing (27) of a semiconductor component (21), preferably a power semiconductor component features a plurality of external leads (1-5). Between adjacent external leads (2-3 and 4-5) for identical supply potentials or signals, mechanically reinforcing flat conductor webs (28 |
| 7615840 |
Device performance improvement using flowfill as material for isolation structures |
November 10, 2009 |
| A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body. |
| 7615807 |
Field-effect transistor structures with gate electrodes with a metal layer |
November 10, 2009 |
| Provided is an integrated circuit including a transistor with a gate electrode. The gate electrode includes a polysilicon layer in contact with a gate dielectric layer separating the gate electrode and a semiconductor substrate that comprises an active region of the transistor. The g |
| 7615770 |
Integrated circuit having an insulated memory |
November 10, 2009 |
| A memory cell includes a first electrode, a second electrode, and phase-change material between the first electrode and the second electrode. The phase-change material defines a narrow region. The memory cell includes first insulation material having a first thermal conductivity and |
| 7615499 |
Method for oxidizing a layer, and associated holding devices for a substrate |
November 10, 2009 |
| A method is presented in which a layer which is to be oxidized is processed, in a single-substrate process. The process temperature during the processing is recorded directly at the substrate or at a holding device for the substrate. The method includes introducing a substrate, which |
| 7615440 |
Capacitor and method of manufacturing a capacitor |
November 10, 2009 |
| In a method of fabricating a semiconductor device, a level of metal is formed within an interval dielectric. The level of metal includes a first metal line separated from a second metal line by a region of the interlevel dielectric. The region of interlevel dielectric is removed betw |
| 7615410 |
Chip-sized flip-chip semiconductor package and method for making the same |
November 10, 2009 |
| A semiconductor package (10; 14) comprises a semiconductor die (2; 2') with a plurality of contact areas (4) on its active surface and an electrically conductive bump (7) on each contact area (4). The die (2; 2') and electrically conductive bumps (7) are encapsulated in a plastic hou |
| 7614023 |
System for estimating a terminal capacitance and for characterizing a circuit |
November 3, 2009 |
| A method for estimating a terminal capacitance associated with a terminal of a cell of a digital circuit includes providing first and second capacitance values associated with an upper and lower bound, respectively, on the terminal capacitance, providing results of a timing analysis |
| 7613224 |
Qualification and selection of the frequency channels for an adaptive frequency hopping method b |
November 3, 2009 |
| In a method for qualification of the transmission quality of a frequency channel in a wire-free communication system that has two or more frequency channels, units in the system communicate via the frequency channels. Data is transmitted in time slots in a time pattern using a time s |
| 7613028 |
Solid electrolyte switching element |
November 3, 2009 |
| A switching element for reversible switching between an electrically insulating OFF state and an electrically conductive ON state, having two electrodes, namely a reactive electrode and an inert electrode, and also a solid electrolyte arranged between the two electrodes, which is cha |
| 7612627 |
Integrated binary phase shift keying with silicon MEMS resonators |
November 3, 2009 |
| A modulator includes a micro-electromechanical resonator device configured to receive an input signal and generate two output signals in response thereto, wherein the two signals having a predetermined phase relationship therebetween. The modulator further includes a switching system |
| 7612457 |
Semiconductor device including a stress buffer |
November 3, 2009 |
| An integrated circuit includes a first surface configured for mounting to a carrier, an active area of the integrated circuit spaced from the first surface, a bond pad disposed over and in electrical communication with the active area, and a ceramic inorganic stress-buffering layer dispo |
| 7612408 |
MOS transistor device |
November 3, 2009 |
| The invention relates to a MOS transistor device of the trench type, in which, in a semiconductor region of a first conductivity type, within a deep gate trench extending in the vertical direction of the semiconductor region, a vertical gate electrode and a gate oxide with a field plate |
| 7612406 |
Transistor, memory cell array and method of manufacturing a transistor |
November 3, 2009 |
| A transistor includes a first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, the gate groove being defined |
| 7612388 |
Power semiconductor element with an emitter region and a stop zone in front of the emitter regio |
November 3, 2009 |
| The power semiconductor element has an emitter region and a stop zone in front of the emitter region. The conductivities of the emitter region and of the stop zone are opposed to one another. In order to reduce not only the static but also the dynamic loss of the power semiconductor fore |
| 7611958 |
Method of making a semiconductor element |
November 3, 2009 |
| A method of producing a capacitor that includes producing a first electrode having a first surface; forming a recess in an element, walls of the element and the first surface of the first electrode defining the recess, the element having a first surface exterior of the recess; formin |
| 7611941 |
Method for manufacturing a memory cell arrangement |
November 3, 2009 |
| In an embodiment of the invention, a method for manufacturing a memory cell arrangement includes forming a charge storing memory cell layer stack over a substrate; forming first and second select structures over, respectively, first and second sidewalls of the charge storing memory c |
| 7610455 |
Technique to read special mode register |
October 27, 2009 |
| Embodiments are provided in which a method and apparatus for accessing a special mode register of a memory device are described. A command to access the special mode register is detected. The command is executed by driving data from the special mode register onto a data bus. The command |
| 7609495 |
Electrostatic discharge (ESD) protection arrangement and ESD protection method |
October 27, 2009 |
| AN ESD protection arrangement is provided which comprises an ESD protection device coupled between a terminal pad of an integrated semiconductor circuit and a supply voltage rail and a compensation loop provided between the terminal pad and an internal circuit node of the ESD protect |
