| Patent Number |
Title Of Patent |
Date Issued |
| 7111125 |
Apparatus and method for renaming a data block within a cache |
September 19, 2006 |
| A microprocessor apparatus is provided that enables exclusive allocation and renaming of a block of cache lines. The apparatus includes translation logic and execution logic. The translation logic translates a block allocate and rename instruction into a micro instruction sequence th |
| 7089371 |
Microprocessor apparatus and method for prefetch, allocation, and initialization of a block of c |
August 8, 2006 |
| A microprocessor apparatus for exclusive prefetch and initialization of cache lines, including translation logic and execution logic. The translation logic translates a block allocate and initialize instruction into a micro instruction sequence that directs a microprocessor to prefet |
| 7089368 |
Microprocessor apparatus and method for exclusively prefetching a block of cache lines from memo |
August 8, 2006 |
| A microprocessor apparatus for exclusive prefetch of a block of data from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended block prefetch instruction into a micro instruction sequence directing a microprocessor to prefetch |
| 7080211 |
Microprocessor apparatus and method for prefetch, allocation, and initialization of a cache line |
July 18, 2006 |
| A microprocessor apparatus for exclusive prefetch and initialization of a cache line from memory, including translation logic and execution logic. The translation logic translates an allocate and initialize instruction into a micro instruction sequence that directs a microprocessor to |
| 7080210 |
Microprocessor apparatus and method for exclusive prefetch of a cache line from memory |
July 18, 2006 |
| A microprocessor apparatus that enables exclusive prefetch of a cache line from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended prefetch instruction into a micro instruction sequence that directs a microprocessor to p |
| 7076639 |
Apparatus and method for masked move to and from flags register in a processor |
July 11, 2006 |
| A method and apparatus are provided for writing to a flags register in a pipeline microprocessor. Responsive to a macro instruction that directs a write to the flags register, a mask is generated using destination information for the write and privilege level information for the write, |
| 7039793 |
Microprocessor apparatus and method for accelerating execution of repeat string instructions |
May 2, 2006 |
| A method and apparatus are provided for processing repeat string instructions with increased efficiency in a processor pipeline. Rather than explicitly generating an initial count register setup micro instruction each time a repeat (REP) prefix in encountered, the processor includes |
| 7000081 |
Write back and invalidate mechanism for multiple cache lines |
February 14, 2006 |
| A microprocessor apparatus is provided that enables write back and invalidation of a block of cache lines from memory. The apparatus includes translation logic and execution logic. The translation logic translates a block write back and invalidate instruction into a micro instruction |
| 6998875 |
Output driver impedance controller |
February 14, 2006 |
| An output driver impedance controller for controlling pull-down impedance of at least one output based on a reference value including a programmable reference impedance generator, at least one output driver coupled to a corresponding output, and an impedance matching controller. The |
| 6993738 |
Method for allocating spare cells in auto-place-route blocks |
January 31, 2006 |
| A method for placing spare cells into an auto-place-route (APR) block of an integrated circuit is disclosed. The list of functional cells to be included in the block is determined along with the netlist. The sum of the areas of the functional cells and the desired spare cell area is used |
| 6990558 |
Microprocessor, apparatus and method for selective prefetch retire |
January 24, 2006 |
| An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. In a first embodiment, a first count of the number of accesses to the prefetched cache line and N second counts of the number of accesses to N lines of a replacement candidate set of the c |
| 6988172 |
Microprocessor, apparatus and method for selectively associating store buffer cache line status |
January 17, 2006 |
| A microprocessor with an apparatus for alleviating the need to maintain coherency between cache line status of a store buffer and a response buffer each storing the same cache line address is disclosed. The store buffers include match bits. When a store operation requires a response |
| 6985999 |
Microprocessor and method for utilizing disparity between bus clock and core clock frequencies t |
January 10, 2006 |
| A microprocessor prioritizes cache line fill requests according to request type rather than issuing the requests in program order. In one embodiment, the request types include blocking accesses at highest priority, non-blocking page table walk accesses at medium priority, and non-blo |
| 6985008 |
Apparatus and method for precisely controlling termination impedance |
January 10, 2006 |
| An impedance controller that controls termination impedance of at least one output based on a reference value including a programmable reference impedance generator, at least one termination logic element, and an impedance matching controller. The programmable reference impedance gen |
| 6983358 |
Method and apparatus for maintaining status coherency between queue-separated functional units |
January 3, 2006 |
| An apparatus and method in a microprocessor having two unaligned functional unit pipelines which enables an instruction queue for the second pipeline to be placed at an intermediate pipeline stage rather than after the stage in the first pipeline that retires instructions. The appara |
| 6965254 |
Dynamic logic register |
November 15, 2005 |
| A dynamic logic register including a dynamic circuit, a delayed inverter, a latching circuit, and a keeper circuit. The dynamic circuit pre-charges a pre-charged node while a clock signal is low and evaluates a logic function to control the state of the pre-charged node when the clock go |
| 6963228 |
Complementary input dynamic logic |
November 8, 2005 |
| A complementary input dynamic logic circuit for evaluating a logic function including an N-channel dynamic circuit, a P-channel dynamic circuit and a pass device. The N-channel dynamic circuit determines a complement of the logic function when a clock signal is high by pulling a first ev |
| 6956405 |
Teacher-pupil flip-flop |
October 18, 2005 |
| A teacher-pupil flip-flop with reduced register delay including a gate circuit, a stack circuit, a keeper circuit, a teacher output circuit, a latch circuit and a pupil output circuit. The gate circuit switches after a setup delay in response to transitions of a clock signal. The stack |
| 6949949 |
Apparatus and method for adjusting the impedance of an output driver |
September 27, 2005 |
| An output impedance bias compensation system for adjusting output impedance of at least one output including a reference impedance generator, an impedance matching controller, at least one output impedance generator, and a programmable bias controller. The reference impedance generator |
| 6931517 |
Pop-compare micro instruction for repeat string operations |
August 16, 2005 |
| A microprocessor apparatus is provided for performing a pop-compare operation. The microprocessor apparatus includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives a macro instruction that prescribes the pop-compar |
| 6928537 |
Split history tables for branch prediction |
August 9, 2005 |
| An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a first table, a second table, and selection logic. The first table stores branch histories for a first set |
| 6924670 |
Complementary input dynamic muxed-decoder |
August 2, 2005 |
| A muxed-decoder circuit including multiple complementary input dynamic circuits and an AND logic gate. Each complementary input dynamic circuit includes a complementary P-logic AND dynamic circuit, a complementary N-logic AND dynamic circuit and a pass device. The complementary P-logic |
| 6903582 |
Integrated circuit timing debug apparatus and method |
June 7, 2005 |
| A timing debug tool for an IC that enables varying the skew of selected edges of a primary clock signal for a controllable number of clock cycles. The debug tool enables identification, isolation and analysis of timing problems on the IC. An IC including programmable clock skew logic tha |
| 6895498 |
Apparatus and method for target address replacement in speculative branch target address cache |
May 17, 2005 |
| An apparatus and method in a pipelined microprocessor for replacing one of two target addresses in a branch target address cache (BTAC) line. If only one of the two entries is invalid, the invalid entry is replaced. If both entries are valid, the least recently used entry is replaced. If |
| 6886093 |
Speculative hybrid branch direction predictor |
April 26, 2005 |
| An apparatus for speculatively predicting the direction of a branch instruction in a pipelined microprocessor in a hybrid fashion. A branch target address cache (BTAC) stores a direction prediction about executed branch instructions. The BTAC is indexed by an instruction cache fetch |
| 6886023 |
Apparatus for generating random numbers |
April 26, 2005 |
| A hardware-based random number generator is provided for incorporation within an integrated circuit. The random number generator includes a first variable frequency oscillator, a second variable frequency oscillator, and frequency variation logic. The first variable frequency oscillator |
| 6871206 |
Continuous multi-buffering random number generator |
March 22, 2005 |
| A multi-buffering apparatus in a random number generator. A microprocessor includes a random number generator that employs multiple buffers for buffering random data bytes generated by the generator. The apparatus maintains a first selector for selecting one of the buffers as the current |
| 6870407 |
Thin gate oxide output drive |
March 22, 2005 |
| An output driver circuit including first and second cascoded scaled P-channel devices coupled to first and second cascoded scaled N-channel devices. The P-channel devices are coupled together at a first node and between an output and a first source voltage having an elevated voltage |
| 6862704 |
Apparatus and method for testing memory in a microprocessor |
March 1, 2005 |
| An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test |
| 6862670 |
Tagged address stack and microprocessor using same |
March 1, 2005 |
| A tag address stack (TAS) for reducing the number of address latches and address comparators needed to insure data coherency in a pipelined microprocessor. The TAS is a small pool of address latches shared among data buffers in the microprocessor that stores a unique set of memory ad |
| 6834024 |
Reduced size multi-port register cell |
December 21, 2004 |
| A multi-ported register cell that reduces the number of metal wires and/or transistors per write port. The cell includes a storage element that stores a bit. Each write port includes three transistors and two wires. The first transistor is coupled to a true input of the storage element. |
| 6832296 |
Microprocessor with repeat prefetch instruction |
December 14, 2004 |
| A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preceded by the REP string |
| 6828827 |
Complementary input dynamic logic for complex logic functions |
December 7, 2004 |
| A complementary input dynamic logic circuit for evaluating a complex logic function including complementary input dynamic logic circuits, P-channel devices, an inverter/driver for providing an inverted clock signal, and N-channel pass devices. Each complementary input dynamic logic circu |
| 6823444 |
Apparatus and method for selectively accessing disparate instruction buffer stages based on bran |
November 23, 2004 |
| A branch control apparatus in a microprocessor. The branch control apparatus includes an instruction buffer having a plurality of stages that buffer cache lines of instruction bytes received from an instruction cache. A multiplexer selects one of the bottom three stages in the instru |
| 6810466 |
Microprocessor and method for performing selective prefetch based on bus activity level |
October 26, 2004 |
| A microprocessor that selectively performs prefetch instructions based upon an indication of future processor bus activity and cache line status. The microprocessor includes a programmable threshold register for storing a threshold value. The threshold value is such that if the depth of |
| 6791564 |
Mechanism for clipping RGB value during integer transfer |
September 14, 2004 |
| A mechanism for, and method of, clipping a red-green-blue (RGB) integer value to an n-bit maximum value and a processor incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a multiplexer having a first input that accepts n low-order bits of the RGB |
| 6754810 |
Instruction set for bi-directional conversion and transfer of integer and floating point data |
June 22, 2004 |
| An apparatus and method for bi-directional format conversion and transfer of data between integer and floating point registers is provided. A floating point register is configured to store floating point data, and integer data, in a variety of numerical formats. Data is moved in and out |
| 6741115 |
Digital level shifter for maintaining gate oxide integrity of scaled driver devices |
May 25, 2004 |
| A digital level shifter for driving the input of a scaled P-channel driver device within a voltage shifted range to preclude gate-oxide breakdown of the scaled driver device. The scaled driver device has an output operative within an elevated voltage range, so that the voltage shifted ra |
| 6725359 |
Address stage logic for generating speculative address operand interim results of preceding inst |
April 20, 2004 |
| An apparatus is presented for expediting the execution of address-dependent micro instructions in a pipeline microprocessor. The apparatus computes a speculative result associated with an arithmetic operation, where the arithmetic operation is prescribed by a preceding micro instruction |
| 6707345 |
Oscillator frequency variation mechanism |
March 16, 2004 |
| A frequency variation apparatus is provided for use in a hardware-based random number generator. The frequency variation apparatus includes sampling frequency variation logic and a sampling frequency oscillator. The sampling frequency variation logic produces a noise signal that corr |
| 6697937 |
Split history tables for branch prediction |
February 24, 2004 |
| An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a first table, a second table, and selection logic. The first table stores branch histories for a first set |
| 6681311 |
Translation lookaside buffer that caches memory type information |
January 20, 2004 |
| A translation lookaside buffer (TLB) that caches memory types of memory address ranges. A data unit includes a TLB which, in addition to caching page table entries including translated page base addresses of virtual page numbers as in a conventional TLB, also caches memory address range |
| 6675287 |
Method and apparatus for store forwarding using a response buffer data path in a write-allocate- |
January 6, 2004 |
| An apparatus for forwarding storehit data within a pipelined microprocessor is provided. The apparatus has a plurality of response buffers that receive data from a bus that couples a system memory to the microprocessor and multiplexing and forwarding logic. When a store instruction gener |
| 6647489 |
Compare branch instruction pairing within a single integer pipeline |
November 11, 2003 |
| An apparatus and method are provided for executing a combined compare-and-branch operation in a single integer pipeline microprocessor. Typically, the compare-and-branch operation is specified by two macro instructions. The first macro instruction, a compare macro instruction, direct |
| 6629234 |
Speculative generation at address generation stage of previous instruction result stored in forw |
September 30, 2003 |
| An apparatus is presented for expediting the execution of address-dependent micro instructions in a pipeline microprocessor. The apparatus computes a speculative result associated with an arithmetic operation, where the arithmetic operation is prescribed by a preceding micro instruction |
| 6622211 |
Virtual set cache that redirects store data to correct virtual set to avoid virtual set store mi |
September 16, 2003 |
| A virtual set cache that avoids virtual set store miss penalty. During a query pass of a store operation, only the untranslated physical address bits of the store address are used to index the cache array. In one embodiment, the untranslated physical address bits select four virtual |
| 6609194 |
Apparatus for performing branch target address calculation based on branch type |
August 19, 2003 |
| A branch target address prediction mechanism is provided. A branch target buffer (BTB) is employed to predict target address only of indirect branch instructions. Return addresses are predicted from a call/return stack and PC-relative branch instructions are predicted by directly calcula |
| 6609191 |
Method and apparatus for speculative microinstruction pairing |
August 19, 2003 |
| An apparatus and method are provided for speculatively pairing micro instructions for parallel execution within a single pipeline of a microprocessor and subsequently splitting the paired micro instructions in the same clock cycle as the pairing if a resource conflict or operand depe |
| 6591343 |
Predecode in parallel with TLB compare |
July 8, 2003 |
| An apparatus and method are provided for determining initial information about a macro instruction prior to decoding of the macro instruction by translation logic within a pipeline microprocessor. The apparatus includes an instruction cache divided into a number of cache ways, each of th |
| 6587929 |
Apparatus and method for performing write-combining in a pipelined microprocessor using tags |
July 1, 2003 |
| A tag-based write-combining apparatus in a microprocessor. The apparatus includes a register that stores the store address of the last write-combinable store passing through the store stage of the pipeline. Tag allocation logic compares the last store address with the store address o |
