| Patent Number |
Title Of Patent |
Date Issued |
| RE38029 |
Wafer polishing and endpoint detection |
March 11, 2003 |
| In a chem-mech polishing process for planarizing insulators such as silicon oxide and silicon nitride, a pool of slurry is utilized at a temperature between 85.degree. F.-95.degree. F. The slurry particulates (e.g. silica) have a hardness commensurate to the hardness of the insulator to |
| D393479 |
Point of sale terminal |
April 14, 1998 |
|
| D381675 |
Point of sale terminal |
July 29, 1997 |
|
| D379825 |
Point of sale terminal |
June 10, 1997 |
|
| D372936 |
Control unit with a printer |
August 20, 1996 |
|
| D371516 |
Enclosure for a brightness sensor |
July 9, 1996 |
|
| D322965 |
Computer lower expansion unit |
January 7, 1992 |
|
| 7231501 |
Method for avoiding aliased tokens during abnormal communications |
June 12, 2007 |
| A data initiator device designates an initial data tag set for tagging data transfers to thereby attach data tags from the designated set to commands directed to data transfers between the data initiator device and a data target device subsequent to the designation of the initial data |
| 7177520 |
System and method of timecode repair and synchronization in MPEG streams |
February 13, 2007 |
| A method, apparatus and article of manufacture is provided for processing a previously encoded MPEG video high-resolution (HR) file and corresponding proxy file, for frame accurate timecode repair and synchronization of individual video frames of the HR and proxy files. Each video fr |
| 7054887 |
Method and system for object replication in a content management system |
May 30, 2006 |
| A system and method in accordance with the present invention provides for replication in a content management system. Replication is provided by utilizing the library server to track the objects to be replicated within the system. The replication is accomplished by adding two tables to t |
| 7016971 |
Congestion management in a distributed computer system multiplying current variable injection ra |
March 21, 2006 |
| A distributed computer system includes links and routing devices coupled between the links and routing frames between the links. Each of the routing devices includes a congestion control mechanism for detecting congestion at the routing device and responding to detected congestion by |
| 7015469 |
Electron holography method |
March 21, 2006 |
| An inline electron holograph method for observing a specimen with a transmission electron microscope having an electron gun, a collimating lens system, two spaced objective lenses, a biprism, and an imaging means comprises the steps of: with the first objective lens forming a virtual |
| 6876557 |
Unified SRAM cache system for an embedded DRAM system having a micro-cell architecture |
April 5, 2005 |
| A unified SRAM cache system is provided incorporated several SRAM macros of an embedded DRAM (eDRAM) system and their functions. Each incorporated SRAM macro can be independently accessed without interfering with the other incorporated SRAM macros within the unified SRAM cache system. Th |
| 6724225 |
Logic circuit for true and complement signal generator |
April 20, 2004 |
| A MOSFET logic circuit for performing a logic AND operation is presented including three transistors, wherein at least two input signals are provided to the circuit and an output signal indicative of an AND operation performed on a first and second input signal of the at least two in |
| 6714476 |
Memory array with dual wordline operation |
March 30, 2004 |
| A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the |
| 6713791 |
T-RAM array having a planar cell structure and method for fabricating the same |
March 30, 2004 |
| A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell |
| 6683805 |
Suppression of leakage currents in VLSI logic and memory circuits |
January 27, 2004 |
| An SRAM system is provided having an array of SRAM cells including at least one circuit receiving a first power voltage and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit. The system is one of a memory array and a |
| 6682786 |
Liquid crystal display cell having liquid crystal molecules in vertical or substantially vertica |
January 27, 2004 |
| A liquid crystal display cell having liquid crystal molecules positioned in a vertical or a substantially vertical alignment is provided. The liquid crystal display cell includes at least two substantially homogeneous fluorinated alignment layers disposed on transparent electrodes; a liq |
| 6675130 |
System and method of using a plurality of sensors for determining an individual's level of produ |
January 6, 2004 |
| A system is provided having a plurality of sensors for affixing to a person's torso, hands, feet, head, etc. The function of each sensor is to determine the distance between itself and the other sensors to ascertain the distance between the hands and feet, for instance, in order to measu |
| 6665642 |
Transcoding system and method for improved access by users with special needs |
December 16, 2003 |
| A system and method for providing transformed web pages to users with special needs is presented. In one aspect of the system and method, a Translator/Mediator Server is located between the user and the web site. The Translator/Mediator Server translates and transforms the web pages |
| 6654414 |
Video conferencing using camera environment panoramas |
November 25, 2003 |
| Image data is communicated from a source system to a target system. At the source system, a background environment map is generated and communicated to the target system. The source system then captures a source image from position and field of view of a camera. In addition, the backgrou |
| 6647008 |
Method and system for sharing reserved bandwidth between several dependent connections in high s |
November 11, 2003 |
| A method for establishing a network connection through a link issuing from a physical port is disclosed. The link has an aggregation of connections. The network connection has a required capacity. The method first computes, from mean bit rates of the aggregation of connections, a mean ag |
| 6639488 |
MEMS RF switch with low actuation voltage |
October 28, 2003 |
| Disclosed is a capacitive electrostatic MEMS RF switch comprised of a lower electrode that acts as both a transmission line and as an actuation electrode. Also, there is an array of one or more fixed beams above the lower electrode that is connected to ground. The lower electrode transmi |
| 6634001 |
Remote monitoring of computer programs |
October 14, 2003 |
| Systems and methods for remotely monitoring the execution of computer programs are provided. Monitoring instructions are added the computer program so that during execution of the program, data may be collected regarding the program execution. The collected data may be automatically |
| 6631503 |
Temperature programmable timing delay system |
October 7, 2003 |
| The present invention provides a temperature programmable timing delay system utilizing circuitry for generating a band-gap reference and for sensing the on-chip temperature of an integrated circuit chip. The circuitry outputs the sensed temperature as a binary output which is receiv |
| 6631141 |
Methods, systems and computer program products for selecting an aggregator interface |
October 7, 2003 |
| Methods, systems and computer program products are provided for which associate physical links of a network device to aggregator ports of the network device where there are more physical links of the network device capable of aggregation than aggregator ports of the network device. P |
| 6627924 |
Memory system capable of operating at high temperatures and method for fabricating the same |
September 30, 2003 |
| A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is copl |
| 6621294 |
Pad system for an integrated circuit or device |
September 16, 2003 |
| The present invention provides a pad system for an integrated circuit or device. The pad system includes logic circuitry having at least one pad input terminal for connecting to at least one pad and at least two output terminals for connecting to the at least one circuit system of the |
| 6618704 |
System and method of teleconferencing with the deaf or hearing-impaired |
September 9, 2003 |
| A system and method is provided for real time teleconferencing, where one of the participants is deaf or hearing-impaired. In one aspect of the system and method, each participant has an Automatic Speech Recognition (ASR) system and a chat service system, such as AOL Instant Messenger.TM |
| 6617702 |
Semiconductor device utilizing alignment marks for globally aligning the front and back sides of |
September 9, 2003 |
| The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one |
| 6617690 |
Interconnect structures containing stress adjustment cap layer |
September 9, 2003 |
| Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first |
| 6614714 |
Semiconductor memory system having a data clock system for reliable high-speed data transfers |
September 2, 2003 |
| A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of |
| 6611678 |
Device and method for trainable radio scanning |
August 26, 2003 |
| A trainable radio scanner, including a station monitoring circuit to scan a plurality of radio frequencies and extract audio samples of a predetermined duration from each one of the plurality of radio frequencies having a signal strength above a reception threshold; a memory storing |
| 6611033 |
Micromachined electromechanical (MEM) random access memory array and method of making same |
August 26, 2003 |
| A micromachined electromechanical random access memory (MEMRAM) array is disclosed which includes a plurality of MEM memory cells, where each MEM memory cell has an MEM switch and a capacitor. The MEM switch includes a contact portion configured for moving from a first position to a seco |
| 6601093 |
Address resolution in ad-hoc networking |
July 29, 2003 |
| A method, system, and computer program product for resolving address information in an ad-hoc networking environment. Two indicators are defined to indicate whether (1) a device has a self-assigned (i.e. auto-configured) IP (Internet Protocol) address and (2) the device has an admini |
| 6574127 |
System and method for reducing noise of congested datalines in an eDRAM |
June 3, 2003 |
| A dataline wiring structural system is provided for an eDRAM which suppresses coupling and switching noise associated with datalines by providing a plurality of metal levels upon which the datalines are positioned. Each of the datalines carrying a differential signal includes at leas |
| 6563736 |
Flash memory structure having double celled elements and method for fabricating the same |
May 13, 2003 |
| A flash memory array having a plurality of bitlines, at least one wordline and a plurality of flash memory flash memory elements, wherein each flash memory element includes two transistors for storing two bits, and wherein each flash memory element is positioned between a pair of adjacen |
| 6556477 |
Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same |
April 29, 2003 |
| A semiconductor memory system fabricated on one substrate is presented including an SRAM device, a DRAM device and a Flash memory device. In one embodiment the SRAM device is a high-resistive load SRAM device. In another embodiment the DRAM device is a deep trench DRAM device. A method |
| 6552398 |
T-Ram array having a planar cell structure and method for fabricating the same |
April 22, 2003 |
| A T-RAM array having a planar cell structure is presented which includes a plurality of T-RAM cells. Each of the plurality of T-RAM cells is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance p+ diffusion region. A silicided |
| 6549450 |
Method and system for improving the performance on SOI memory arrays in an SRAM architecture sys |
April 15, 2003 |
| The present invention provides an SOI SRAM architecture system which holds all the bitlines at a lower voltage level, for example, ground, or a fraction of Vdd, during array idle or sleep mode. Preferably, the bitlines are held at a voltage level approximately equal to Vdd minus Vth, whe |
| 6545935 |
Dual-port DRAM architecture system |
April 8, 2003 |
| A dual-port, folded-bitline DRAM architecture system is presented which prioritizes two simultaneous access requests slated for a DRAM cell of a data array prior to performing at least one of the access requests to prevent affecting the integrity of the data while suppressing noise due t |
| 6542973 |
Integrated redundancy architecture system for an embedded DRAM |
April 1, 2003 |
| An integrated redundancy eDRAM architecture system for an embedded DRAM macro system having a wide data bandwidth and wide internal bus width is disclosed which provides column and row redundancy for defective columns and rows of the eDRAM macro system. Internally generated column and ro |
| 6540674 |
System and method for supervising people with mental disorders |
April 1, 2003 |
| A system and method for supervising persons with a mental illness, the method comprising the steps of acquiring sensor data related to the person and the person's environment; tracking the acquired sensor data; and recognizing changes in the sensor data indicating the occurrence of an |
| 6539434 |
UOWE's retry process in shared queues environment |
March 25, 2003 |
| An UOWE is created to represent a message which is put out to the coupling facility. If it is a committed message and the PUT failed for some reason, the UOWE is flagged for "retry". These retry UOWEs will accumulate over time. The retry logic analyzes each "retry" UOWE, extracts the log |
| 6531911 |
Low-power band-gap reference and temperature sensor circuit |
March 11, 2003 |
| A combined low-voltage, low-power band-gap reference and temperature sensor circuit is provided for providing a band-gap reference parameter and for sensing the temperature of a chip, such as an eDRAM memory unit or CPU chip, using the band-gap reference parameter. The combined sensor ci |
| 6528984 |
Integrated compliant probe for wafer level test and burn-in |
March 4, 2003 |
| The present invention is directed to a structure comprising a substrate having a surface; a plurality of elongated electrical conductors extending away from the surface; each of said elongated electrical conductors having a first end affixed to the surface and a second end projecting awa |
| 6525731 |
Dynamic view-dependent texture mapping |
February 25, 2003 |
| A system for providing interactive views of 3-dimensional models with surface properties is disclosed. The system provides a compact representation of a 3D model and its surface features and provides for efficiently viewing and interacting with the model using dynamically switched te |
| 6523040 |
Method and apparatus for dynamic and flexible table summarization |
February 18, 2003 |
| A method for performing table summarization. In a data network requests arrive at random from viewing devices (i.e., PC, PDA, laptop, etc.) to view objects which oftentimes contain large tables. The table summarization method compresses the rows/columns of the large tables in additio |
| 6507237 |
Low-power DC voltage generator system |
January 14, 2003 |
| A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded |
| 6504204 |
Compact dual-port DRAM architecture system and method for making same |
January 7, 2003 |
| The present invention provides a process integration technique which significantly reduces the array size of dual-port DRAM architecture systems. The array is reduced to a size which is significantly smaller than the array size of prior art DRAM architecture systems by using bitlines |
