| Patent Number |
Title Of Patent |
Date Issued |
| 6797135 |
Electroplating apparatus |
September 28, 2004 |
| The present invention relates to a method of forming a conductive layer and an electroplating device, and in particular, to a method of forming a conductive layer that provides an electrically-conductive layer having both characteristics of increased adhesiveness to an electroplated body |
| 6753564 |
Capacitor of semiconductor device and method of fabricating the same |
June 22, 2004 |
| A capacitor of a semiconductor device is provided which includes a semiconductor substrate and insulating interlayer formed on the semiconductor substrate. The insulating interlayer has a contact hole which exposes a portion of the semiconductor substrate. A plug fills in the contact |
| 6664614 |
Lead frame and bottom lead semiconductor package using the lead frame |
December 16, 2003 |
| A lead frame includes a pair of guide rails separated at a predetermined space; at least one dam bar for connecting the pair of guide rails; a die paddle for mounting a semiconductor chip between the dam bar; a tie bar for supporting the die paddle; a plurality of leads each consisting o |
| 6583054 |
Method for forming conductive line in semiconductor device |
June 24, 2003 |
| Provided with a method for forming conductive lines in a semiconductor device including the steps of: (a) forming a first conductive line on a substrate; (b) forming a first insulating layer on the substrate as well as on the first conductive line; (c) etching the first insulating layer |
| 6511890 |
Method of fabricating a semiconductor device |
January 28, 2003 |
| The present invention related to a method of fabricating a semiconductor device which prevents short channel hump due to the moisture in an insulating interlayer. The present invention includes the steps of forming a trench typed field oxide layer defining an active area in a field area |
| 6502214 |
Memory test circuit |
December 31, 2002 |
| A memory test circuit in a test mode divides a plurality of mats forming a memory and coupled with identical global input/output lines into even and odd-numbered mats and simultaneously activates the even or odd-numbered mats. The memory test circuit sequentially amplifies the activated |
| 6458627 |
Semiconductor chip package and method of fabricating same |
October 1, 2002 |
| A semiconductor chip package and a method of fabricating a semiconductor chip package provide a reduced chip size package. The semiconductor chip package includes a semiconductor chip; a plurality of pads disposed on an upper surface of the semiconductor chip; a thermosetting resin forme |
| 6372116 |
Method of forming a conductive layer and an electroplating apparatus thereof |
April 16, 2002 |
| The present invention relates to a method of forming a conductive layer and an electroplating device, and in particular, to a method of forming a conductive layer that provides an electrically-conductive layer having both characteristics of increased adhesiveness to an electroplated body |
| 6358794 |
Capacitor of semiconductor device and method of fabricating the same |
March 19, 2002 |
| A capacitor of a semiconductor device is provided which includes a semiconductor substrate, an insulating interlayer formed on the semiconductor substrate, the insulating interlayer having a contact hole which exposes a predetermined portion of the semiconductor substrate, a plug fil |
| 6340636 |
Method for forming metal line in semiconductor device |
January 22, 2002 |
| A method for forming a metal line in a semiconductor device, in which a resolution is improved for securing a design rule and minimizing a difference of critical dimensions, including the steps of (1) forming a first insulating film and a second insulating film on a substrate, (2) et |
| 6297091 |
Method for fabricating contact pad for semiconductor device |
October 2, 2001 |
| A method for fabricating a contact pad for a semiconductor device, including the steps of forming device isolation layers in a semiconductor substrate to define active regions, forming a plurality of wordlines crossing the active regions, forming an insulating layer on an entire surf |
| 6225820 |
Semiconductor device having improved input buffer circuit |
May 1, 2001 |
| An input buffer circuit for a semiconductor device includes a first input buffer unit having first and second transistors, a second input buffer unit coupled to the first input buffer unit, the second input buffer unit having third and fourth transistors, a control unit for activating on |
| 6192160 |
Hardware architectures for image dilation and erosion operations |
February 20, 2001 |
| A hardware architecture for mathematical morphology operations such as dilation and erosion of an image signal is provided. A hardware architecture for an image dilation operation includes: a plurality of adders corresponding to the size of the structuring element for adding the imag |
| 6146932 |
Method for fabricating metal-oxide-semiconductor field effect transistor device |
November 14, 2000 |
| A method for fabricating a metal-oxide-semiconductor field effect transistor (MOSFET) device, includes: a step of dividing a semiconductor substrate into an active region and an isolation region; a step of forming a first insulation layer on the semiconductor substrate; a step of forming |
| 6125064 |
CAS latency control circuit |
September 26, 2000 |
| A CAS latency control circuit for a SDRAM is provided for improving operation speeds of first and second CAS latencies. The circuit includes a controlling circuit unit for receiving a clock signal and providing first, second, third, and fourth control signals, a first latch for either |
| 6104656 |
Sense amplifier control circuit in semiconductor memory |
August 15, 2000 |
| A sense amplifier control circuit in a semiconductor memory supplies a sense amplifier with two power source voltages with voltage levels different from each other, successively. A first logic gate is supplied with a pair of sense amplifier enabling bar signals which are applied to t |
| 6104637 |
Apparatus for programming threshold voltage for non-volatile memory cell and method therefor |
August 15, 2000 |
| An apparatus for programming a threshold-voltage of a non-volatile memory cell includes a reference voltage generator means applying a predetermined voltage to a word line of a reference memory cell having the same electric characteristics as the memory cell desired to be programmed and |
| 6097635 |
Sensing circuit for programming/reading multilevel flash memory |
August 1, 2000 |
| A sensing circuit for programming/reading a multilevel flash memory includes a voltage controller for controlling a voltage being applied to a drain of a selected cell, a reference voltage generator for generating a reference voltage, a comparator with its one terminal applied by the |
| 6094389 |
Semiconductor memory apparatus having refresh test circuit |
July 25, 2000 |
| A semiconductor memory apparatus having a refresh test circuit provided with a control unit, a write control unit, a row address buffer and column address buffer, a refresh address counter, a refresh control unit, a column decoder, a data input/output buffer, a plurality of sense amplifi |
