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Hyundai Electronics Industries Co., Ltd. Patents
Assignee:
Hyundai Electronics Industries Co., Ltd.
Address:
Kyoungki-Do, KR
No. of patents:
1873
Patents:












Patent Number Title Of Patent Date Issued
6430100 Redundancy circuitry for repairing defects in packaged memory having registers August 6, 2002
A redundancy circuitry is used in a memory device for repairing defects in a packaged memory having registers by using antifuse. The redundancy circuitry includes: an anticell for storing data to be replaced; a temporary anticell for storing the data temporarily; a row and a column a
6429453 Substrate assembly for burn in test of integrated circuit chip August 6, 2002
Disclosed is a substrate used in performing a burn-in test of the integrated circuit chip prior to packaging the chip and a method for manufacturing a known good die using the same. The substrate includes a body having a plurality of through holes; a plurality of metal lines formed o
6429140 Method of etching of photoresist layer August 6, 2002
A method of forming a patterned photoresist layer is performed in a nitrogen gas atmosphere. The method includes the steps of sequentially forming a layer to be etched and first photoresist layer on a semiconductor substrate, and sequentially forming an intermediate barrier layer and
6429074 Semiconductor memory device and method for fabricating the same August 6, 2002
A method for fabricating a semiconductor memory device using a silicon-on-insulator device, including forming a semiconductor memory device capable of reducing the topology between a cell region and a peripheral region and preventing floating body effect.
6426897 Method of erasing a flash memory device July 30, 2002
A method of erasing a flash memory device performs erase operation by hot carrier injection method, by applying a ground potential to a source and applying the bias from a high voltage to a low voltage step by step, with a voltage of 5V being applied to a drain, wherein the bias of a flo
6424568 Code addressable memory cell in flash memory device July 23, 2002
A code addressable memory (CAM) included in a flash memory device comprises a unit cell including a floating gate and a control gate; and a gate coupling unit coupled to the unit cell or further comprises a switching circuit for connecting and disconnecting the unit cell with the gate
6424349 Data controller with a data converter for display panel July 23, 2002
A data controller for a display panel includes a first memory for storing video data, a second memory for storing next video data, a control unit for controlling the first memory and the second memory for one of storing and outputting the video data stored in at least one of the first an
6423637 Method of manufacturing copper wiring in a semiconductor device July 23, 2002
A method of manufacturing copper wiring in a semiconductor device by forming a diffusion prevention film on a damascene pattern, forming a first copper film by a PVD method, forming a second copper film by a spin-on coating method, and forming a third copper film by a PVD or electroc
6423610 Method for forming inner capacitor of semiconductor devices using oxide layers formed through a July 23, 2002
A method for forming an inner capacitor of a semiconductor device. The method comprises steps of forming an interlayer insulation layer over a semiconductor substrate, wherein a plurality of layers to form semiconductor transistors are formed on the semiconductor substrate; forming a
6423554 Semiconductor device having a capacitor and method for the manufacture thereof July 23, 2002
A semiconductor device for use in a memory cell including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure formed on top of the first insulating layer, composed of a bottom electrode, a capacitor thin film placed
6421386 Method for coding digital moving video including gray scale shape information July 16, 2002
A method for coding a digital moving video including gray scale shape information. Picture-unit overhead information is first transmitted and it is then determined whether a video packet to be coded is a first packet of a given picture. A video packet header including overhead informatio
6421330 Apparatus and method for expanding service area of CDMA mobile communication system July 16, 2002
An apparatus and method for expanding a service area of a code division multiple access (CDMA) system restricted in terms of timing. The service area of a CDMA mobile communication system, which is defined by a radius longer than a radius of a communication supported area, namely, a cell
6421278 Method of improving an electrostatic discharge characteristic in a flash memory device July 16, 2002
There is disclosed a method of improving an electrostatic discharge ("ESD") characteristic in a flash memory device. In order to prevent generation of leak current caused when charges generated upon a testing of the ESD are introduced into an internal circuit, the prevent can prevent a c
6420241 Method for forming an isolation region in a semiconductor device and resulting structure using a July 16, 2002
A method for forming an element isolation film of a semiconductor device and the semiconductor device. A pad insulator is constructed on a semiconductor substrate. An over-etching process is performed to recess the semiconductor substrate to a predetermined depth while giving a pad i
6420234 Short channel length transistor and method of fabricating the same July 16, 2002
Transistor and method for fabricating the same, which can form a channel length shorter than a lithography limit and adjust a substrate impurity concentration variably, the method including the steps of (1) depositing an insulating film on a semiconductor substrate and forming a trench t
6418043 Circuit for driving nonvolatile ferroelectric memory July 9, 2002
A circuit for driving a non-volatile ferroelectric memory is provided in which a driver has a boost circuit that simplifies a wordline driver and applies a boosted voltage to a wordline without loss of a threshold voltage. The driving circuit increases a current driving capability and
6417101 Method for manufacturing semiconductor memory device incorporating therein copacitor July 9, 2002
A method for manufacturing a semiconductor device for use in a memory cell including the steps of preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conducti
6417067 Method for fabricating an electrode structure of capacitor for semiconductor device July 9, 2002
An electrode structure and fabrication method for a capacitor for a semiconductor memory device which have been improved suitably for the formation of a high dielectric thin film, which method includes forming an interlayer insulation film on a substrate having a transistor formed th
6417042 Method of manufacturing a capacitor in a semiconductor device July 9, 2002
There is disclosed a method of manufacturing a capacitor in a semiconductor device. In a Ta.sub.2 O.sub.5 capacitor using a Ru lower electrode, the method processes the Ru lower electrode at low temperature before a Ta.sub.2 O.sub.5 film of a dielectric film is deposited, so that Ru
6415152 METHOD FOR OPERATING BASE STATION TO SOLVE SPEECH DISABLE STATE BASED ON INTER-SPEECH SPHERE MOV July 2, 2002
A method for operating a base station to solve a speech disable state based on the inter-speech sphere movement of a mobile station in enlarging a speech radius limited in timing in a CDMA mobile communication system. In a base station where a speech radius wider than that limited by a m
6414621 Analog to digital converter having a parallel converter and logic for generating serial data July 2, 2002
An analog to digital converter (ADC) circuit suitable for processing serial data at a fast rate includes a clock control block for receiving a reference strobe signal REF_STB, a reference clock signal REF_CLK, and number of bit control signals CONT.sub.-- 1, CONT.sub.-- 2. The clock
6414348 Method for fabricating capacitor in semiconductor device July 2, 2002
The present invention is directed to a method for fabricating a capacitor in a semiconductor device. The capacitor uses a Ta.sub.2 O.sub.5 film as a dielectric film. The method for fabrication can include forming a nitride film on a capacitor lower electrode by a rapid thermal nitration
6413787 Method for fabricating dielectric film July 2, 2002
A method for fabricating a dielectric film can increase capacitance by etching a film generated by annealing for preprocess using NO gas. The method for fabricating the dielectric film includes: a step for performing a first annealing on a silicon lower electrode, and forming a first
6411547 Nonvolatile memory cell and method for programming and/or verifying the same June 25, 2002
Nonvolatile memory device and a method of programming the same, is disclosed, wherein, for single level or multi-level programming of a cell, predetermined voltages are applied to a control gate, source and drain respectively for varying a charge amount in the floating gate. A channel
6411127 Multi-level bonding option circuit June 25, 2002
The present invention relates to a bonding option circuit and a multi-level buffer that generates a plurality of selection signals from a single selective condition applied to a bonding pad to reduce the number of required bonding pads and buffers for a semiconductor device. A multi-
6410390 Nonvolatile memory device and method for fabricating the same June 25, 2002
Disclosed is a nonvolatile memory device comprising a semiconductor substrate defining first and second active regions arranged in one direction; a first gate insulating layer and a floating gate deposited on the first and second active regions in a predetermined pattern; a second ga
6410382 Fabrication method of semiconductor device June 25, 2002
A fabrication method of a semiconductor device improves the hot carrier immunity and prevents the deterioration of electrical characteristics of p-channel transistors. The fabrication method of the semiconductor device includes: sequentially forming a gate insulating film and a gate
6410344 Ferroelectric random access memory device and method for the manufacture thereof June 25, 2002
A ferroelectric random access memory (FeRAM) device including an active matrix provided with a transistor and diffusion regions, a first capacitor structure formed on a portion of the active matrix and provided with a first capacitor thin film made of strontium bismuth tantalate (SBT), a
6408415 Test mode setup circuit for microcontroller unit June 18, 2002
A test mode setup circuit for a microcontroller unit (MCU) operates a test mode for an internal circuit or the like using only a reset pin and a clock pin, which are required pins. Thus, the microcontroller uses the test mode setup circuit without providing a separate test pin. The test
6407962 Memory module having data switcher in high speed memory device June 18, 2002
In a memory module having a plurality of memory chips and a plurality of data switchers on one board, wherein each data switcher is selectively turned on or off in response to a switcher control signal to connect corresponding memory chip with a common data bus line, an apparatus for
6407947 Method of erasing a flash memory device June 18, 2002
Methods of erasing a flash memory device are disclosed. After performing a first erasure operation, the methods perform a second erasure operation wherein an erasure pulse width or an erasure voltage is increased if the number of erased cells is below a predetermined number of erased cel
6407005 Method for forming semiconductor device to prevent electric field concentration from being gener June 18, 2002
A method for fabricating a field oxide layer capable of being applied to highly integrated circuits. The semiconductor device according to the present invention prevents electric field concentration at the corners of the active region, by filling a recess generated in a field oxide layer
6406973 Transistor in a semiconductor device and method of manufacturing the same June 18, 2002
The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P.sup.+ salicide forming technology having an elevated channel and a source/drain using the selective SiGe epi-silicon growth technology. It
6404680 Circuit to check overerasing of repair fuse cells June 11, 2002
The present invention comprises a first means to select all repair fuse cells, using a test mode, and to sense each repair fuse cell state depending on the applied read-out voltage; a logical means to generate decision signals to decide the overerasing state of said repair fuse cells
6403435 Method for fabricating a semiconductor device having recessed SOI structure June 11, 2002
A semiconductor device having a recessed silicon on insulator (SOI) structure includes an SOI substrate having a cell region, a peripheral region and a field region, the SOI substrate having a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second
6403419 Method of manufacturing a flash memory device June 11, 2002
There is disclosed a method of manufacturing a flash memory device by which an insulating film spacer is formed on both sidewalls of a gate electrode and a drain region is then formed. Thus, the present invention can improve coverage during a deposition process for forming a select gate
6403156 Method of forming an A1203 film in a semiconductor device June 11, 2002
A method is disclosed for forming an aluminum oxide film on a semiconductor device. In a process of depositing an aluminum oxide film by atomic layer deposition method using TMA (trimethyl aluminum; Al(CH.sub.3).sub.3) as an aluminum source and H.sub.2 O as an oxygen reaction gas, the di
6400636 Address generator for a semiconductor memory June 4, 2002
The present invention related to a semiconductor memory that prevents malfunctions by simplifying input paths of an address decoder and by controlling an output timing of a decoded internal address signal. The present invention includes an address signal generator producing complemen
6400216 Multi-driving apparatus by a multi-level detection and a method for controlling the same June 4, 2002
A multi-driving apparatus by a multi-level detection which pluralizes a voltage detection level in order to effectively operate voltage generators in the voltage generation circuit, minimizes a level fluctuation, reduces noise influenced on a total operation of the apparatus, increases a
6399986 Semiconductor device and method of fabricating the same June 4, 2002
The present invention relates to a semiconductor device and a method of fabricating the same. A semiconductor device having first and second transistor regions and a field region includes a semiconductor substrate having a first type conductivity, a first trench in the substrate at the
6399488 Method of manufacturing a contact plug in a semiconductor device June 4, 2002
A method of manufacturing a contact plug in a semiconductor device is disclosed. In-situ thermal doping of an impurity such as phosphorous (P) during the process by which polysilicon for a contact plug is formed by selective growth method and after in-situ doping after the growth process
6396957 Method and apparatus for generating a bounding rectangle of a VOP for interlaced scan type video May 28, 2002
A method and apparatus for generating a bounding rectangle of a VOP for interlaced scan type video signals, which are capable of accurately generating a bounding rectangle, thereby preventing a color bleeding from occurring in the field-based chrominance shape subsampling. The method
6396322 Delay locked loop of a DDR SDRAM May 28, 2002
A delay locked loop is disclosed which is capable of operating at both of a rising edge and a falling edge of a clock. The delay locked loop includes: a first differential amplifier receiving a clock at a positive input and an inverted clock at a negative input for buffering; a second di
6395601 Method for forming a lower electrode for use in a semiconductor device May 28, 2002
A method for manufacturing a semiconductor device can form a thick lower electrode made of Pt. The method begins with the preparation of an active matrix provided with at least one diffusion region and an insulating layer formed thereon. Thereafter, the insulating layer is patterned into
6395581 BGA semiconductor package improving solder joint reliability and fabrication method thereof May 28, 2002
A BGA semiconductor package including: a semiconductor chip on which a chip pad is formed; a flexible member formed on the semiconductor chip; a metal pattern formed on one surface of the flexible member; a connection member for electrically connecting the pad and the metal pattern; and
6392929 Method of programming a flash memory cell May 21, 2002
There is disclosed a method of programming a flash memory cell, which is performed applying a given voltage a gate and a drain and maintaining a source and a substrate at a ground potential. The method variably applies a given voltage, with two or more steps, to one of the gate and drain
6392917 Nonvolatile ferroelectric memory and method for fabricating the same May 21, 2002
A ferroelectric memory and method for fabricating the same includes a plurality of first gate electrodes and second gate electrodes formed on an active region of a substrate electrically separated form each other, a plurality of first electrodes of first ferroelectric capacitors each
6392475 Offset compensation apparatus in a differential amplifier circuit and offset compensation method May 21, 2002
The present invention relates to an offset compensation apparatus in a differential amplifier circuit and an offset compensation method thereof that can compensate an offset in a differential amplifier circuit separately for each input signal. The offset compensation device preferabl
6392456 Analog mixed digital DLL May 21, 2002
An analog mixed digital DLL includes a digital mode controller and an analog mode controller. The digital mode controller compares phases of delay clock signals outputted from a plurality of delay blocks and a first clock signal, detects an initial locking point, selects one delay clock
6392287 Semiconductor package and fabricating method thereof May 21, 2002
The present invention relates to a semiconductor package and a fabricating method thereof, more particularly, to a chip size package of a wafer level and a fabricating method thereof. Accordingly, the present invention eases sufficiently the thermal stress generated from the difference o

 
 
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