| Patent Number |
Title Of Patent |
Date Issued |
| RE37413 |
Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
October 16, 2001 |
| A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads |
| D447127 |
Portable telephone |
August 28, 2001 |
|
| D446197 |
Portable telephone |
August 7, 2001 |
|
| D445770 |
Portable telephone |
July 31, 2001 |
|
| D303110 |
Disk drive |
August 29, 1989 |
|
| D302151 |
Monitor for computer |
July 11, 1989 |
|
| D297139 |
Television receiver |
August 9, 1988 |
|
| 7426311 |
Object-based coding and decoding apparatuses and methods for image signals |
September 16, 2008 |
| An object-based coding apparatus and method for image signals, wherein upon scanning shape-adaptive transform coefficients of an input image signal transformed in accordance with a shape-adaptive transform, only segments containing such shape-adaptive transform coefficients are scann |
| 7233046 |
Semiconductor device and fabrication method thereof |
June 19, 2007 |
| A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized |
| 7193902 |
Method of erasing a flash memory cell |
March 20, 2007 |
| Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor |
| 7122401 |
Area array type semiconductor package fabrication method |
October 17, 2006 |
| An area array type semiconductor package includes a plurality of conductive media such as solder bumps or solder balls, attached to respective bond pads of a chip. The conductive media act as external output terminals. The chip is attached to a lead frame by a thermal conductive adhe |
| 7095087 |
Semiconductor device and fabrication method thereof |
August 22, 2006 |
| A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized |
| 7088772 |
Method and apparatus for updating motion vector memories |
August 8, 2006 |
| A method and apparatus for updating motion vector memories used for prediction of motion vectors in a video compression coding/decoding method and system. For a frame composed of N macroblocks in the horizontal direction, only (2N+1) motion vector memories are used to store all motio |
| 7078956 |
Charge pump circuit |
July 18, 2006 |
| A charge pump circuit is disclosed which can perform high pumping by changing the condition of connection of the charge pump circuit by connecting a serial and parallel switching circuit and a level shift circuit between unit charge pumps to construct the charge pump circuit. |
| 7072226 |
Method of erasing a flash memory cell |
July 4, 2006 |
| Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor |
| 7071068 |
Transistor and method for fabricating the same |
July 4, 2006 |
| A transistor and a method for fabricating the same that involves a forming a device isolation oxide film semiconductor substrate, forming an opening in the device isolation oxide to open the substrate and define an active region, the junction between the oxide and the substrate having a |
| 7057656 |
Pixel for CMOS image sensor having a select shape for low pixel crosstalk |
June 6, 2006 |
| A novel CMOS image unit pixel layout having a photodiode including an optically optimized square image sensing region. The square image sensing layout provides for reduced electrical and color crosstalk and improved modulation transfer function (MTF) between neighboring pixels of an arra |
| 7053434 |
Ferroelectric memory device and method of making the same |
May 30, 2006 |
| A ferroelectric memory device, e.g., nonvolatile, has an effective layout by eliminating a separate cell plate line. The ferroelectric memory device includes first and second split word lines formed over first and second active regions of a semiconductor substrate, and the first and |
| 7026704 |
Semiconductor device for reducing plasma charging damage |
April 11, 2006 |
| A semiconductor device and method of manufacturing the semiconductor device including a semiconductor substrate of a first conductivity type. A scribe lane area formed in the substrate to define chip formation areas. A deep well area formed in each chip formation area. The deep well |
| 7013413 |
Method for compressing output data and a packet command driving type memory device |
March 14, 2006 |
| The present invention relates to a packet command driving type memory device, a method for compressing output data according to the present invention is characterized to write first data of a certain bit in a corresponding address of core cell regions, read the first data of a certai |
| 7012001 |
Method for manufacturing a semiconductor device for use in a memory cell that includes forming a |
March 14, 2006 |
| A semiconductor device for use in a memory cell includes an active matrix provided with a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate and conductive plugs electrically connected to the transistors, a number of bottom electrodes formed on top |
| 6969617 |
Method for manufacturing NAND type nonvolatile ferroelectric memory cell |
November 29, 2005 |
| NAND type non-volatile ferroelectric memory cell and non-volatile ferroelectric memory of the same, in which numbers of access to a main cell and a reference cell are made the same, to maintain bitline induced voltages by the reference cell and by the main cell constant, for improvin |
| 6949441 |
Ferroelectric memory device and method of making the same |
September 27, 2005 |
| A ferroelectric memory device, e.g., nonvolatile, has an effective layout by eliminating a separate cell plate line. The ferroelectric memory device includes first and second split word lines formed over first and second active regions of a semiconductor substrate, and the first and seco |
| 6937653 |
Rate control apparatus and method for real-time video communication |
August 30, 2005 |
| A rate control apparatus for real-time video communication includes: an initialization unit for setting an initial value required for rate control according to a transmission speed and the number of input frames; a target bit calculation unit for obtaining the target number of encoding b |
| 6936880 |
Capacitor of semiconductor memory device and method of manufacturing the same |
August 30, 2005 |
| A capacitor and a method of manufacturing the same are disclosed. The BST dielectric film is disposed between the lower electrode by coating a sidewall of the upper electrode and then forming the lower electrode in a second contact hole defined by the upper electrode and BST film. As suc |
| 6933196 |
Isolation structure and method for semiconductor device |
August 23, 2005 |
| A device isolation structure and method for a semiconductor device according to the present invention includes forming first and second trenches by etching predetermined regions of a semiconductor substrate, forming a buried insulating film in the trenches, filling in the trenches by |
| 6927438 |
Nonvolatile ferroelectric memory device and method for fabricating the same |
August 9, 2005 |
| A nonvolatile ferroelectric memory device and a method for fabricating the same are provided that increase a process margin and simplify process steps. In addition, a number of masks is reduced to save the cost and at the same time minimize or reduce a layout area. The nonvolatile fe |
| 6914632 |
Apparatus for panning and scaling window in image sensor |
July 5, 2005 |
| An apparatus for panning and scaling a window in CMOS image sensor is described. The apparatus comprises a pixel array having a plurality of unit pixels, a row driving part, an analog-digital converting part, an address generating part for generating a row address and a column address |
| 6912245 |
Apparatus for calculating decision parameters in an IMT-2000 system |
June 28, 2005 |
| Improved techniques for calculating decision parameters in an IMT-2000 system is disclosed. In an apparatus for calculating decision parameters, there is provided a correlation value calculation unit having a number of correlation value calculators, each of which calculates a correlation |
| 6903414 |
Semiconductor memory having channel regions at sides of a trench |
June 7, 2005 |
| Semiconductor memory and method for fabricating the same, the semiconductor memory including a cell transistor having a trench region formed in a semiconductor substrate and channel regions at sides of the trench region, source/drain regions formed in a bottom of the trench region and in |
| 6900064 |
Method for manufacturing NAND type nonvolatile ferroelectric memory cell |
May 31, 2005 |
| NAND type non-volatile ferroelectric memory cell and non-volatile ferroelectric memory of the same, in which numbers of access to a main cell and a reference cell are made the same, to maintain bitline induced voltages by the reference cell and by the main cell constant, for improvin |
| 6893922 |
Non-volatile memory device and manufacturing method thereof |
May 17, 2005 |
| A non-volatile memory device and a manufacturing method thereof are disclosed. The non-volatile memory device includes a gate insulating film formed on a semiconductor substrate, a floating gate formed on the gate insulating film, a dielectric film comprising a (TaO).sub.1-x (TiO).sub.x |
| 6892220 |
Apparatus and method for creating a link and checking link validity for objects by storing a tim |
May 10, 2005 |
| An apparatus and method for checking a link validity in a computer network, wherein, for the linking and referencing from one multimedia document to a different multimedia document in the computer network, desired information of the different multimedia document, such as last modified ti |
| 6885103 |
Semiconductor device including ternary phase diffusion barrier |
April 26, 2005 |
| A method for manufacturing a semiconductor device can simply form a silicide film for reducing ohmic contact between a metal line and a substrate and a ternary phase thin film as an amorphous diffusion prevention film between a metal line and the silicide film. The method for manufac |
| 6885070 |
Semiconductor memory device and fabrication method thereof |
April 26, 2005 |
| In a semiconductor memory device including memory cells and a peripheral circuit unit, a memory cell has a first gate structure formed on a semiconductor substrate; a first impurity region of a first conductive type formed in the substrate on a first side of the gate structure; and a |
| 6870769 |
Decoder circuit used in a flash memory device |
March 22, 2005 |
| A decoder circuit according to the present invention comprises a global row decoder consisted of a first decoding means selected according to a row address signal and a second decoding means to which an output signal of the first decoding means and an erasure signal are input and a local |
| 6867804 |
Image sensor for implementing data read operation at high speed |
March 15, 2005 |
| An image sensor is an apparatus for sensing a light beam to generate a digital image data. The image sensor includes a pixel array for sensing a light beam to generate an analog image data, a control and interface unit for managing an interface with external circuits and generating contr |
| 6867109 |
Mask set for compensating a misalignment between patterns and method of compensating a misalignm |
March 15, 2005 |
| The present invention discloses a mask set for compensating for a misalignment between the patterns and method of compensating for a misalignment between the patterns. A mask set of the present invention comprises a first mask consisted of a mask substrate on which a main pattern and |
| 6859675 |
Semiconductor factory automation system and method for monitoring at least one server in real ti |
February 22, 2005 |
| A method for monitoring at least one server in a semiconductor factory automation (FA) system, includes the steps of: a) providing server state information from at least one server to a real-time database, wherein the server state information includes an availability of a central process |
| 6849506 |
Non-volatile memory device and fabrication method |
February 1, 2005 |
| A non-volatile memory device includes a floating gate formed over a semiconductor substrate. At one end of the floating gate, there is a tapered protrusion having a horn-like or bird's beak shape. A control gate covers the floating gate except for the tapered protrusion. Sidewall spa |
| 6841394 |
Nonvolatile ferroelectric memory device and method for fabricating the same |
January 11, 2005 |
| A nonvolatile ferroelectric memory device and a method for fabricating the same are provided that increase a process margin and simplify process steps. In addition, a number of masks is reduced to save the cost and at the same time minimize or reduce a layout area. The nonvolatile fe |
| 6833592 |
Latch-up resistant CMOS structure |
December 21, 2004 |
| Provided with a semiconductor device including: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the first conductivity type form |
| 6831863 |
Array of flash memory cells and data program and erase methods of the same |
December 14, 2004 |
| The present invention relates to an array of flash memory cells whose unit cell includes a single transistor of MONOS/SONOS structure (Metal/poly-Silicon Oxide Nitride Oxide Semiconductor) and to data programming and erasing using the same. The array of the flash memory cells include |
| 6828686 |
Chip size stack package and method of fabricating the same |
December 7, 2004 |
| A chip size stack package includes two semiconductor chips arranged such that their bond pads-forming surfaces are opposed and insulating layers are applied thereto. Via-holes for exposing bond pads are formed in the insulating layers. Metal traces exposed at both sides of the insulating |
| 6821850 |
Method of manufacturing a multi-level flash EEPROM cell |
November 23, 2004 |
| A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an |
| 6821690 |
Photomask and method for forming micro patterns of semiconductor device using the same |
November 23, 2004 |
| A photomask including chromium patterns divided into two groups in such a fashion that the chromium patterns in one of the two chromium pattern groups alternate, one by one, with the chromium patterns in the other chromium pattern group, the chromium patterns being formed on two quartz |
| 6819676 |
Method for improving scheduling fairness of signal transmission/reception in a network |
November 16, 2004 |
| A method for improving scheduling fairness in using a network may include detecting whether or not a collision occurs during packet transmission in the network having a plurality of nodes; and storing and monitoring signal transmit/receive states before the collision with respect to each |
| 6813723 |
Method of compensating for delay between clock signals |
November 2, 2004 |
| Method of compensating for a delay between clock signals for a semiconductor integrated circuit having a plurality of devices synchronous to a plurality of clock signals, including the steps of (1) searching for devices between which a data transmission path is set up synchronous to |
| 6813657 |
Apparatus for processing a bit stream |
November 2, 2004 |
| A bit stream processing apparatus is provided which stores a bit stream in a circular buffer without separately storing a header and data of the bit stream. The bit stream processing apparatus includes: a circular buffer for storing a transmitted bit stream; a first register for indicati |
| 6803251 |
Integrated device package and fabrication methods thereof |
October 12, 2004 |
| The present invention relates to a chip sized integrated circuit package. A device package embodying the invention includes: an insulative substrate having a plurality of conductive first lands formed on an upper surface of the substrate and a plurality of conductive second lands formed |
