| Patent Number |
Title Of Patent |
Date Issued |
| 7298650 |
Page buffer for a programmable memory device |
November 20, 2007 |
| A page buffer is provided for an electrically programmable memory that includes multiple memory cells forming multiple memory pages. The page buffer includes a register for at least temporarily storing data read from or to be written to the memory cells of a selected memory page. The |
| 7298645 |
Nano tube cell, and semiconductor device having nano tube cell and double bit line sensing struc |
November 20, 2007 |
| The present invention discloses a nano tube cell, and a semiconductor device having the nano tube cell and a double bit line sensing structure. The cell array circuit includes a plurality of top sub cell arrays, a plurality of bottom sub cell arrays, a main bit line sense amp and a word |
| 7298189 |
Delay locked loop circuit |
November 20, 2007 |
| The DLL circuit detects a frequency of an external clock signal and adjusts a coarse delay during a DLL circuit operation, thereby quickly terminating a feedback operation of the DLL circuit and having a reduced circuit area of a delay line. Therefore, the DLL circuit can be used for |
| 7298157 |
Device for generating internal voltages in burn-in test mode |
November 20, 2007 |
| The disclosure is a device for applying a test voltage from the external of a memory device in a burn-in test mode. An internal voltage generator for a burn-in test is comprised of pad means receiving an external voltage, switching means turned on in the burn-in test mode, and an int |
| 7297593 |
Method of manufacturing a floating gate of a flash memory device |
November 20, 2007 |
| A method of forming a floating gate of a flash memory device wherein a hard mask nitride film is stripped using two or more etching steps. Accordingly, a seam can be prevented when depositing a floating gate polysilicon film. Furthermore, the floating gate polysilicon film may be bla |
| 7297572 |
Fabrication method for electronic system modules |
November 20, 2007 |
| This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid |
| 7295482 |
Semiconductor memory device for a low voltage operation |
November 13, 2007 |
| A semiconductor memory includes first and second cell arrays for applying a data signal onto pairs of first bit lines and second bit lines, respectively, first and second reference cell blocks each of which applies a reference signal onto a corresponding bit line bar or a correspondi |
| 7289591 |
Counter circuit for controlling off-chip driver |
October 30, 2007 |
| Disclosed herein is a counter circuit for controlling an off-chip driver, wherein hexadecimal number counting is performed using a N (N is a natural number) number of T-flip-flops. The plurality of the T-flip-flops performs a hexadecimal number counting operation to generate 4-bit, 5-bit |
| 7289364 |
Programmable memory device with an improved redundancy structure |
October 30, 2007 |
| An electrically programmable memory device is proposed including: a matrix of memory cells arranged in a plurality of memory arrays and at least one redundancy array; and a substituting structure that substitutes the use of each memory array with the use of one of the at least one redund |
| 7289251 |
Image sensor |
October 30, 2007 |
| An image sensor is disclosed, in which the image sensor changes the diameter of a lens from the center area of a chip to an edge thereof to obtain uniform sensitivity as a whole. The image sensor includes a plurality of light-receiving portions for converting a signal corresponding t |
| 7288364 |
Top anti-reflective coating composition and method for pattern formation of semiconductor device |
October 30, 2007 |
| Disclosed herein is a top anti-reflective coating composition which comprises a photoacid generator represented by Formula 1 below. ##STR00001## wherein n is between 7 and 25. Since the top anti-reflective coating composition dissolves a portion of a photoacid generator present a |
| 7286418 |
Internal voltage supply circuit |
October 23, 2007 |
| Disclosed herein is an internal voltage supply circuit for a semiconductor device. The internal voltage supply circuit includes a first voltage driver for supplying a first voltage in response to a first enable signal, a second voltage driver for supplying a second voltage in respons |
| 7286331 |
Electrostatic protection device for semiconductor device |
October 23, 2007 |
| Disclosed is an electrostatic protection device for a semiconductor device, which protects the semiconductor device from damage due to electrostatic discharge (ESD). The electrostatic protection device includes a delivery unit for inducing the static electricity introduced to the inp |
| 7286171 |
Apparatus and method for concealing defective pixels in image sensors having test mode |
October 23, 2007 |
| An apparatus and method for concealing defective pixels in image sensors having a test mode. The image sensing apparatus includes a sensing module for capturing an image from an object, wherein the sensing module includes a plurality of pixels and a light source for detecting a defect |
| 7286000 |
Semiconductor device |
October 23, 2007 |
| A semiconductor device can accurately control the timings of various signals used in the semiconductor device using a simple configuration. The semiconductor device includes first fuse units which output first fuse signals, respectively, a first decoder which receives the first fuse |
| 7285485 |
Method for forming a gate in a semiconductor, which prevents gate leaning caused by thermal proc |
October 23, 2007 |
| A method for forming a gate in a semiconductor device includes the steps of: providing a substrate having active and field regions; selectively etching a portion of the active region to form a trench; forming on the substrate including the trench an amorphous conductive film for forming |
| 7285370 |
Light absorbent agent polymer useful for organic anti-reflective coating, its preparation method |
October 23, 2007 |
| Disclosed are a light absorbent agent polymer for organic anti-reflective coating which can prevent diffused light reflection of bottom film layer or substrate and reduce standing waves caused by a variation of thickness of the photoresist itself, thereby, increasing uniformity of the |
| 7283415 |
Apparatus for controlling activation period of word line of volatile memory device and method th |
October 16, 2007 |
| An apparatus for controlling an activation period of a word line of a volatile memory device is disclosed. The apparatus adjusts the activation period of the word line using a member for adjusting a pulse width of a pulse signal that activates the word line according to an operation mode |
| 7283388 |
Memory device using multiple layer nano tube cell |
October 16, 2007 |
| A memory device features a multiple layer nano tube cell. In the memory device, a cross point cell array including a capacitor and a PNPN nano tube switch is effectively arranged to reduce the whole memory size. Also, in the memory device, the nano tube cell array including a capacit |
| 7283383 |
Phase change resistor cell, nonvolatile memory device and control method using the same |
October 16, 2007 |
| A nonvolatile memory device features a phase change resistor cell as a cross-point cell using a phase change resistor and a serial diode switch. The phase change resistor has logic data corresponding to a crystallization state changed by the amount of current supplied from a word lin |
| 7282977 |
Duty cycle correction device |
October 16, 2007 |
| Enclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first signal, a phase splitter |
| 7282956 |
High voltage switching circuit of nonvolatile memory device |
October 16, 2007 |
| A high-voltage switching circuit comprises: a high-voltage switch configured to transfer a high voltage; a pumping circuit configured to boost signals of first, second, and third nodes by conducting pumping operations in response to a plurality of clock signals; and a drive signal tr |
| 7282421 |
Methods for reducing a thickness variation of a nitride layer formed in a shallow trench isolati |
October 16, 2007 |
| A method for reducing a thickness variation of a nitride layer in a shallow trench isolation (STI) CMP process is provided, the method including forming an active region pattern in an alignment key region of a scribe lane where a device isolation film is formed at an ISO level, and f |
| 7282420 |
Method of manufacturing a flash memory device |
October 16, 2007 |
| A method of manufacturing a flash memory device wherein a stacked structure of an oxide and nitride or the reverse is applied to insulation spacers provided on sidewalls of gates for forming source/drain regions. After completing the source/drain regions, spacers are formed on sidewa |
| 7282318 |
Photoresist composition for EUV and method for forming photoresist pattern using the same |
October 16, 2007 |
| The present invention relates to photoresist compositions for EUV and methods for forming photoresist patterns. More specifically, fine photoresist patterns: of less than 50 nm without collapse are formed with EUV (Extreme Ultraviolet) as an exposure light source by using a negative |
| 7280422 |
BLEQ driving circuit in semiconductor memory device |
October 9, 2007 |
| A bit line equalization signal (BLEQ) driving circuit for generating an equalization signal used to perform a precharge operation in a semiconductor memory device includes a second boosted voltage generator for producing a second boosted voltage by pumping a supply voltage, a BLEQ dr |
| 7280418 |
Internal voltage generation control circuit and internal voltage generation circuit using the sa |
October 9, 2007 |
| An internal voltage generation control circuit and an internal voltage generation circuit using the same are provided. The internal voltage generation control circuit comprises first to n-th latches and a logic unit. The first latch receives, as an input signal, a column active pulse |
| 7280402 |
Method for reading flash memory cell, NAND-type flash memory apparatus, and NOR-type flash memor |
October 9, 2007 |
| A method of reading a flash memory cell, a NAND-type flash memory apparatus, and/or a NOR-type flash memory apparatus improves the resolution capability and reduces the determination time by using different voltages applied at the read operation of the flash device. As a result, it i |
| 7280135 |
Pixel array, image sensor having the pixel array and method for removing flicker noise of the im |
October 9, 2007 |
| There are provided a pixel array capable of detecting and removing a flicker noise, an image sensor employing the pixel array and an automatic flicker noise detecting method capable of effectively detecting and removing the flicker noise of the image sensor. For the purpose, a pixel |
| 7279955 |
Reference voltage generating circuit |
October 9, 2007 |
| A reference voltage generating circuit for outputting a reference voltage having a level varying depending on the operation mode of a semiconductor device is disclosed. The reference voltage generating circuit includes a first reference voltage generator that outputs first and second ini |
| 7279933 |
Output driver circuit |
October 9, 2007 |
| The present invention relates to an output driver circuit for a semiconductor memory device, in particular, a memory device using a DDR II concept or a concept similar thereto, which can reduce a variation in the slew rate of an output driver thereof between maximum and minimum value |
| 7279691 |
Ion implantation apparatus and method for implanting ions by using the same |
October 9, 2007 |
| Disclosed are an ion implantation apparatus and a method for implanting ions by using the same. The ion implanter for implanting ions into a wafer, includes: a first quadrupole magnet assembly for focusing an ion beam transmitted from an ion beam source; a scanner for deflecting the |
| 7279394 |
Method for forming wall oxide layer and isolation layer in flash memory device |
October 9, 2007 |
| Disclosed herein are methods for forming wall oxide films in flash memory devices and methods for forming isolation films. After trenches are formed in the substrate, an ISSG (In-Situ Steam Generation) oxidization process is performed to form wall oxide films on sidewalls of the tren |
| 7279388 |
Method for manufacturing transistor in semiconductor device |
October 9, 2007 |
| Disclosed is a method for manufacturing a transistor in a semiconductor device, which can improve a device's refresh characteristics. The method includes: providing a silicon substrate having active and field regions; performing a channel ion implantation into the substrate; sequentially |
| 7279256 |
Photoresist polymer and photoresist composition containing the same |
October 9, 2007 |
| Photoresist polymers and photoresist compositions are disclosed. A photoresist polymer comprising a polymerization repeating unit represented by Formula I is less sensitive to change in the amount of energy due to its higher active energy than that of a conventional photoresist polym |
| 7277977 |
DRAM for high-speed data access |
October 2, 2007 |
| A DRAM with a general interleaving scheme for data input/output uses a normal bank structure. The DRAM provides a high-performance without consideration of a data access pattern. In order to implement the high-performance, the DRAM includes a plurality of normal banks, at least one c |
| 7276959 |
Pumping circuit of semiconductor device |
October 2, 2007 |
| A pumping circuit of a semiconductor device includes a power supply unit for supplying a power source voltage to a first node, a first transfer pump for transferring a first electric potential of the first node to a second node, a first pumping unit coupled to the first node for pumping |
| 7276930 |
Circuit and method for detecting skew of transistor in semiconductor device |
October 2, 2007 |
| A circuit and method for easily detecting skew of a transistor within a semiconductor device are provided. The circuit for detecting the skew of the transistor includes a linear voltage generating unit for outputting a linear voltage by using a first supply voltage, a first attenuation u |
| 7276758 |
Non-volatile memory having three states and method for manufacturing the same |
October 2, 2007 |
| Disclosed is a non-volatile memory having three data states and a method for manufacturing the same. The non-volatile memory includes a silicon substrate having a device separation film; a floating gate formed on the silicon substrate; a tunnel oxide film interposed between the silicon |
| 7276725 |
Bit line barrier metal layer for semiconductor device and process for preparing the same |
October 2, 2007 |
| The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose an ion implantation |
| 7276451 |
Method for manufacturing semiconductor device |
October 2, 2007 |
| Disclosed herein is a method for manufacturing a semiconductor device. According to the present invention, a bit line contact region and a storage node contact region are simultaneously formed, and then a storage node contact hole is formed after a form of bit line to reduce a height |
| 7276443 |
Method for forming metal wiring in semiconductor device |
October 2, 2007 |
| Disclosed is a method for forming a metal wiring in a semiconductor device in order to improve the operational speed of the semiconductor device. The method includes the steps of depositing an interlayer dielectric film on a silicon substrate, in which the interlayer dielectric film has |
| 7274593 |
Nonvolatile ferroelectric memory device |
September 25, 2007 |
| A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is |
| 7273781 |
Method of forming a capacitor in a semiconductor device without wet etchant damage to the capaci |
September 25, 2007 |
| To form a capacitor in a semiconductor device, an etching barrier layer and a mold insulating layer are sequentially formed on an interlayer insulating film having a contact plug. A hole exposing the contact plug is formed by etching the mold insulating layer and the etching barrier |
| 7272056 |
Data output controller in semiconductor memory device and control method thereof |
September 18, 2007 |
| A data output controller of a high-speed memory device and a method therefore. The data output controller includes a first section for detecting a unit delay multiple of an external clock signal based on the external clock signal and a delay circuit of the external clock signal, a se |
| 7271669 |
Voltage controlled oscillator and phase locked loop circuit having the same |
September 18, 2007 |
| A voltage controlled oscillator and a phase locked loop circuit having the same reduce power consumption by using charges leaked into a ground voltage terminal for an output driving operation with characteristics of both output terminals having different phases in a unit delay cell. The |
| 7271439 |
Semiconductor device having pad structure for preventing and buffering stress of silicon nitride |
September 18, 2007 |
| The present invention discloses a semiconductor device having a pad structure for preventing a stress of a silicon nitride film. The semiconductor device includes a semiconductor substrate, a lower structure formed on the semiconductor substrate, a first insulation film formed on the |
| 7271088 |
Slurry composition with high planarity and CMP process of dielectric film using the same |
September 18, 2007 |
| Disclosed herein are a CMP slurry composition with high-planarity and a CMP process for polishing a dielectric film using the same. More specifically, a CMP slurry composition with high-planarity includes a carbon compound having tens of thousands of carboxyl groups and having a mole |
| 7271066 |
Semiconductor device and a method of manufacturing the same |
September 18, 2007 |
| Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate pre-cleaning process. |
| 7270937 |
Over-coating composition for photoresist and process for forming photoresist pattern using the s |
September 18, 2007 |
| Overcoating compositions for a photoresist and methods of using the same are disclosed. More specifically, overcoating compositions for a photoresist comprising materials which can weaken acid stably are disclosed. These materials neutralize large amounts of acid produced in the uppe |
