| Patent Number |
Title Of Patent |
Date Issued |
| 7033955 |
Method for fabricating a semiconductor device |
April 25, 2006 |
| The present invention discloses a method for fabricating a semiconductor device wherein precursor and deposition conditions of a bit line hard mask nitride film and a spacer nitride film are varied so that the nitride films are formed to have different etching ratios for sufficient p |
| 7033907 |
Method for forming isolation layer of semiconductor device |
April 25, 2006 |
| A method for forming an isolation layer of a semiconductor device is disclosed, which comprises the steps of: etching a silicon substrate having a cell region and a peripheral circuit region, forming a first trench having a first size in the cell region, and forming a second trench h |
| 7033732 |
Method of preparing anti-reflective coating polymer and anti-reflecting coating composition comp |
April 25, 2006 |
| Disclosed are an organic anti-reflective coating polymer having a structure represented by the following formula I which is introduced to the top portion of photoresist, its preparation method and an anti-reflective coating composition, in a process for forming ultra-fine patterns of |
| 7033729 |
Light absorbent agent polymer for organic anti-reflective coating and preparation method and org |
April 25, 2006 |
| Disclosed are a light absorbent agent polymer for organic anti-reflective coating which can prevent diffused reflection of lower film layer or substrate and reduce standing waves caused by variation of thickness of the photoresist itself, thereby, increasing uniformity of the photoresist |
| 7032084 |
Circuit for generating column selection control signal in memory device |
April 18, 2006 |
| A circuit for generating a Yi control signal in a memory device. The circuit comprises a column select signal control block for generating a Yi control signal for a normal operation of a first cycle of a page mode, a latch for setting the Yi control signal from the column select signal |
| 7031216 |
Refresh controller with low peak current |
April 18, 2006 |
| The disclosure relates to a memory such as a DRAM (dynamic random access memory), specifically to a refresh controller embedded in a memory. The refresh controller according to the present invention lowers the levels of peak currents by differentiating active times of a first bank enable |
| 7031210 |
Method of measuring threshold voltage for a NAND flash memory device |
April 18, 2006 |
| Provided is a method of measuring threshold voltages in a NAND flash memory device. In the method, a test voltage is applied to a wordline of selected memory cells to measure a distribution profile of threshold voltages of memory cells. A voltage summing up a pass voltage and an oper |
| 7031200 |
Data output apparatus for memory device |
April 18, 2006 |
| A data output circuit for a memory device improves data transfer speed from the memory device by re-amplifying stored data using by a bitline sense amplifier and transferring it to global input/output lines. Data read from the memory device is coupled to an amplifier interposed between |
| 7031190 |
Structure for testing NAND flash memory and method of testing NAND flash memory |
April 18, 2006 |
| Provided is a structure for testing a NAND flash memory including a first string select transistor for controlling transfer of a voltage inputted via a first bit line; a first string having a plurality of flash memory cells, connected between the first string select transistor and a firs |
| 7031186 |
Biosensor and sensing cell array using the same |
April 18, 2006 |
| A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a ma |
| 7030901 |
Methods and apparatus for removing NTSC signals from a digital television signal |
April 18, 2006 |
| A method and apparatus for removing national television system committee (NTSC) signals from a broadcasted datastream including advanced television system committee (ATSC) signals are provided. The apparatus includes an NTSC signal removing unit for removing the NTSC signal from an i |
| 7030684 |
High voltage switch circuit of semiconductor device |
April 18, 2006 |
| The present invention discloses a high voltage switch circuit of a semiconductor device which can efficiently switch a high voltage over about 20V required in a flash memory even in a low voltage below about 1.4V by reducing increase of a threshold voltage by a back bias, facilitate |
| 7030671 |
Circuit for controlling pulse width |
April 18, 2006 |
| The present invention discloses a circuit for controlling a pulse width including a frequency detection circuit for extracting an operation frequency band by receiving an external clock, delaying the external clock for a different time and comparing a frequency of the external clock |
| 7030507 |
Test pattern of semiconductor device |
April 18, 2006 |
| Disclosed is a test pattern comprising: lower metal patterns for test formed in such a manner that crank-type patterns are arranged in sequence overlapping on each other in a view along a vertical line; hole patterns formed in such a manner that each of the hole patterns exposes either a |
| 7030036 |
Method of forming oxide layer in semiconductor device |
April 18, 2006 |
| Provided is related to a method of forming an oxide layer of a semiconductor device. In the method, a first oxide layer is formed with a first thickness on a semiconductor substrate, that is comparted into first and second fields, and then a second oxide layer is formed on the first |
| 7030013 |
Method for fabricating semiconductor device using high dielectric material |
April 18, 2006 |
| Disclosed is a method for fabricating a semiconductor device using high dielectric material. The method comprises the steps of: forming an Hf thin film on a silicon substrate; oxidizing the Hf thin film by performing an oxidizing process; and performing an annealing process after the |
| 7030006 |
Method for forming contact hole and spacer of semiconductor device |
April 18, 2006 |
| Disclosed is a contact hole forming method capable of reducing parasitic capacitance between a conductive layer patterns, preventing bad contacts caused by mask misalignment and effectively filling an interlayer insulating layer between the conductive layer patterns. The method inclu |
| 7029999 |
Method for fabricating transistor with polymetal gate electrode |
April 18, 2006 |
| The present invention is related to a method for fabricating a transistor with a polymetal gate electrode structure. The method includes the steps of: forming a gate insulation layer on a substrate; forming a patterned gate stack structure on the gate insulation layer, wherein the patter |
| 7029989 |
Semiconductor device and method of manufacturing the same |
April 18, 2006 |
| The present invention relates to a semiconductor device and a method of manufacturing the same. The minimum marginal width of an impurity diffusion layer is defined to reduce by a given width. The reduced width of the impurity diffusion layer is compensated for through a silicon grow |
| 7027351 |
Negative word line driver |
April 11, 2006 |
| Provided is directed to a negative word line driver, including: a block select address generation unit for generating first and second block select addresses having a block information according to an active signal; a row decoder controller for generating a control signal to disable |
| 7027330 |
Multi-input/output repair method of NAND flash memory device and NAND flash memory device thereo |
April 11, 2006 |
| A multi-I/O repair method of a NAND flash memory device and a NAND flash memory device thereof are disclosed. A NAND flash memory device is disclosed in which page buffers are positioned at the top and bottom of a main array and a redundancy array and have different data lines. The t |
| 7027089 |
Image sensor with defective pixel address storage |
April 11, 2006 |
| Image sensors and methods to construct and use image sensors are disclosed. In an example, an image sensor includes a pixel array, a data store to store data transmitted from the pixel array, an image signal processing unit to perform signal processing on the output of the data store |
| 7026859 |
Control circuit for delay locked loop |
April 11, 2006 |
| Provided is directed to a delay locked loop control circuit capable of reducing a test time and preventing a yield from being reduced, by preventing a failure due to a charge sharing and a failure in a specific frequency and voltage due to a noise of a feedback clock, by means of inc |
| 7026250 |
Method for reducing contact resistance of a semiconductor device |
April 11, 2006 |
| A method for fabricating a semiconductor device wherein the lower portion of a contact hole is cleaned, and doped with an impurity for reducing contact resistance is disclosed. The method comprises: sequentially forming a buffer layer and an interlayer insulating film on a semiconduc |
| 7026213 |
Method of fabricating flash memory device |
April 11, 2006 |
| The present invention relates to a method of fabricating a flash memory device. According to the present invention, an oxide film is deposited and etched to form trenches, the trenches are filled with a metal film, and the metal film undergoes CMP to form bit lines. In this case, an etch |
| 7026199 |
Transistor of semiconductor device and method for manufacturing the same |
April 11, 2006 |
| Transistor of semiconductor device and method for manufacturing the same are disclosed. The transistor comprises a channel region formed on a sidewall of a silicon fin extruding above a device isolation region. The silicon fin serves as an active region and is shorter in length so as to |
| 7023254 |
Duty ratio corrector, and memory device having the same |
April 4, 2006 |
| The present invention discloses a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio |
| 7022624 |
Semiconductor device and method of fabricating the same |
April 4, 2006 |
| The present invention is provided to a semiconductor device and a method of fabricating the same. A spacer consisting of SiCxHy or SiOCxHy having a low dielectric constant is formed at the sidewall of a trench or a hole that is formed in an interlayer insulating film. It is therefore pos |
| 7022599 |
Method of manufacturing semiconductor devices |
April 4, 2006 |
| A method of manufacturing a semiconductor device is disclosed. The method includes depositing an O.sub.3-TEOS oxide film having a good flow-like property under a high adhesive force in order to prevent degradation in the characteristic of the surface of a lower insulating film made of a |
| 7022458 |
Photoresist polymer and photoresist composition containing the same |
April 4, 2006 |
| Photoresist polymers and photoresist compositions are disclosed. A photoresist polymer represented by Formula 1 and a photoresist composition containing the same have excellent etching resistance, thermal resistance and adhesive property, and high affinity to an developing solution, |
| 7019417 |
Power-on reset circuit with current detection |
March 28, 2006 |
| There is provided a power-on reset circuit for generating a power-on reset signal regardless of a power-up slope using not an RC delay method but a current detection method. The power-on reset circuit includes: a power supply voltage sensing node; a power supply voltage detecting unit |
| 7019370 |
Method for manufacturing magnetic random access memory |
March 28, 2006 |
| The present invention discloses an MRAM wherein a write word line is disposed between every other set of the word lines and a ground line is disposed between every other bit lines. This structure of MRAM in accordance with the present invention, Which is similar to folded bit line DR |
| 7018935 |
Method of forming metal line of semiconductor device |
March 28, 2006 |
| Disclosed herein is a method of forming a metal line of a semiconductor device. The method includes forming a metal line connected to an underlying element by, for example, performing a main etching process and an over-etching process, at the same time, forming a metal fuse of which |
| 7018931 |
Method of forming an isolation film in a semiconductor device |
March 28, 2006 |
| Disclosed is a method of forming an isolation film in a semiconductor device. In the process of forming a stack structure of a pad oxide film and a pad nitride film that expose a semiconductor substrate in an isolation region, protrusions of a tail profile are formed at the bottom si |
| 7018930 |
Method for fabricating semiconductor device |
March 28, 2006 |
| A method for fabricating a semiconductor device capable of minimizing deformations of a photoresist pattern and losses of a hard mask. The method includes the steps of: forming an insulating layer for a hard mask on an etch-target layer; forming a sacrificial layer on the insulating |
| 7018927 |
Method for forming isolation film for semiconductor devices |
March 28, 2006 |
| An isolation film for semiconductor devices is formed from a pad oxide film and a pad nitride film on a substrate, etching the pad nitride film, the pad oxide film and the substrate to form a trench in an active region of the substrate; forming a sidewall oxide film on the surface of the |
| 7018924 |
CMP slurry compositions for oxide films and methods for forming metal line contact plugs using t |
March 28, 2006 |
| CMP slurries for oxide film and a method for forming a metal line contact plug of a semiconductor device are described herein. When a polishing process of a multi-layer film is performed by using the disclosed CMP slurry for oxide film including an HXO.sub.n compound (wherein n is an |
| 7018921 |
Method of forming metal line in semiconductor device |
March 28, 2006 |
| The present invention relates to a method of forming a metal line in a semiconductor device, in which an etch-stopping layer is deposited between the interlayer insulation films and then over-etching is performed by using the etch-stopping layer as an etching barrier during the etchi |
| 7018905 |
Method of forming isolation film in semiconductor device |
March 28, 2006 |
| The present invention relates to a method of forming an isolation film of a semiconductor device. According to the present invention, the method includes the steps of forming a pad film on a semiconductor substrate, and patterning the pad film of a predetermined region and a predetermine |
| 7018885 |
Method of manufacturing semiconductor devices |
March 28, 2006 |
| Disclosed is a method of manufacturing semiconductor devices. Before the threshold voltage ion is implanted, an inert ion having no electrical properties is implanted into the bottom of a channel region to form an anti-diffusion layer. Therefore, it is possible to prevent diffusion of |
| 7016256 |
Data input unit of synchronous semiconductor memory device, and data input method using the same |
March 21, 2006 |
| Provided is a data input unit of a synchronous semiconductor memory device comprising: means for generating a rising edge signal and a falling edge signal at a rising edge and a falling edge of a data strobe signal DQS to be input; means for generating a second falling edge signal whenev |
| 7016229 |
Page buffer for NAND flash memory |
March 21, 2006 |
| A page buffer for an NAND flash memory, including: a first latch for loading data; a second latch for storing data stored on a cell depending on a bit line selection signal; a setting circuit for setting the first latch to a high level to load data in a high level; a first switching |
| 7016220 |
Magneto-resistive random access memory |
March 21, 2006 |
| A magneto-resistive random access memory (MRAM) stably read data stored in an MRAM cell in a magnetization direction of a variable magnetic layer of an MTJ element. The MRAM includes a first current sinking circuit to convert a current flowing to a sense amplifier node through a current |
| 7015743 |
Circuit of redundancy IO fuse in semiconductor device |
March 21, 2006 |
| Provided is related to a redundancy IO fuse circuit of a semiconductor device. The redundancy IO fuse circuit is advantageous to enhancing an overall processing speed of a redundancy operation by preventing a voltage drop by a threshold voltage due to an NMOS transistor, by reducing |
| 7015737 |
Delay locked loop circuit capable of operating in a low frequency |
March 21, 2006 |
| A delay-locked loop circuit may include a frequency doubler for increasing a frequency of a clock signal and a frequency divider for decreasing the frequency of the clock signal. The delay-locked loop circuit can be selectively operated in a low frequency and a high frequency by the |
| 7015731 |
CMOS output buffer circuit |
March 21, 2006 |
| A CMOS output buffer circuit comprises an input unit, a compensation control unit, a first switching unit and a second switching unit. The input unit outputs a data signal in response to a stop signal for determining transmission of the data signal. The compensation control unit dete |
| 7015531 |
FeRAM having bottom electrode connected to storage node and method for forming the same |
March 21, 2006 |
| A FeRAM device in which a bottom electrode of a ferroelectric capacitor is connected to a source/drain region of a transistor and a top electrode is connected to a plate line. The FeRAM device comprises a semiconductor substrate; a gate electrode formed on the semiconductor substrate; an |
| 7015099 |
Method of manufacturing a flash memory cell capable of increasing a coupling ratio |
March 21, 2006 |
| A method of manufacturing a flash memory cell. The method includes controlling a wall sacrificial oxidization process, a wall oxidization process and a cleaning process of a trench insulating film that are performed before/after a process of forming the trench insulating film for bur |
| 7015097 |
Method of manufacturing flash memory device |
March 21, 2006 |
| Provided relates to a method of a flash memory device, which performs a first rapid thermal oxidation process at a H.sub.2 rich atmosphere for recovering an etched damage during a gate forming process, and performs a second rapid thermal oxidation process at the H.sub.2 rich atmosphere f |
| 7012851 |
Nonvolatile ferroelectric memory device with split word lines |
March 14, 2006 |
| The present invention relates to a memory device; and, more particularly, to a cell array of a nonvolatile ferroelectric memory device and an apparatus and a method for driving such a cell array. The nonvolatile ferroelectric memory device according to the present invention includes: |
