| Patent Number |
Title Of Patent |
Date Issued |
| 7082179 |
Clock divider of delay locked loop |
July 25, 2006 |
| A divider of a DLL(delay locked loop) measures tAC for various periods due to variation of process, temperature and a supply voltage and provides a divided clock having an optimum tAC. The clock divider includes a clock dividing unit, a test mode clock providing unit and a normal mode cl |
| 7082068 |
Semiconductor memory device and method for adjusting internal voltage thereof |
July 25, 2006 |
| A semiconductor memory device improves test reliability by suppressing unnecessary leakage component in a USMC test which checks if data is normally transferred by extending a time margin between an active signal input time and a bit line sensing time. The semiconductor memory device |
| 7081784 |
Data output circuit of memory device |
July 25, 2006 |
| A data output circuit of a memory device comprises an output enable signal generating unit, an output driving unit, an output driving unit and an output enable control unit. The output enable signal generating unit generates a reference output enable signal in response to a read command |
| 7081779 |
Reset signal generating circuit |
July 25, 2006 |
| The present invention discloses a reset signal generating circuit including a power sensing stabilizing unit, a pull-up driving unit, a voltage adjusting unit, a feedback control unit, a pull-up control unit, a self pull-up bias unit and a self bias unit. The reset signal generating |
| 7081396 |
Method for manufacturing device isolation film of semiconductor device |
July 25, 2006 |
| The present invention discloses method for manufacturing device isolation film wherein a high selectivity slurry containing M.sub.xP.sub.yO.sub.z is used for polishing nitride film to prevent the generation of moat. In accordance with the method, a pad oxide film and a pad nitride film |
| 7081390 |
Semiconductor device and a method of manufacturing the same |
July 25, 2006 |
| Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate pre-cleaning process. |
| 7081325 |
Photoresist polymer and photoresist composition including the same |
July 25, 2006 |
| Photoresist polymers and photoresist compositions containing the same are disclosed. A negative photoresist composition containing a photoresist polymer comprising a repeating unit represented by Formula 4 prevents collapse of patterns when photoresist patterns of less than 50 nm are |
| 7079411 |
Ferroelectric nonvolatile code data output device |
July 18, 2006 |
| A ferroelectric nonvolatile code data output device comprises a code bus command processing unit, a code bus decoder unit, a function block unit, a code bus, a data buffer and a data selecting unit. The ferroelectric nonvolatile code data output device for outputting code data stored in |
| 7079410 |
Ferroelectric memory cell array and device for operating the same |
July 18, 2006 |
| A ferroelectric memory cell array and a device for driving the same are disclosed, in which the ferroelectric memory cell array is defined as first and second cell regions each using at least one group of four split wordlines to reduce a layout area of the memory cell array and/or a RC |
| 7078957 |
Internal voltage generator of semiconductor device comprising characteristic controller |
July 18, 2006 |
| An internal voltage generator of a semiconductor device features a tuning unit, a characteristic controller and an internal voltage generating unit. The tuning unit receives a test mode signal, an external signal and a signal stored in an internal setup device, and outputs a control |
| 7078949 |
Analog delay locked loop having duty cycle correction circuit |
July 18, 2006 |
| An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs; and a second block for receiving the reference clock signal to generat |
| 7078339 |
Method of forming metal line layer in semiconductor device |
July 18, 2006 |
| The present invention is provided to form a metal line layer in a semiconductor device, wherein at least one conductive layer of a plurality of conductive layers is etched, a side wall oxide film is formed on side walls of some conductive layers of the etched conductive layers, and t |
| 7078332 |
Method for manufacturing semiconductor device |
July 18, 2006 |
| The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate on which cell strings are formed and in which a plurality of conductive regions are formed; sequentially forming a first interlayer insulation |
| 7076013 |
Clock synchronization device |
July 11, 2006 |
| A clock synchronization device is disclosed which optimizes clock skew without increasing the number of unit delay cells by using an auxiliary delay circuit when a clock signal of ultra low frequency is inputted and improves operation frequency by using different programmable dividers to |
| 7075853 |
Semiconductor memory device including internal clock doubler |
July 11, 2006 |
| A semiconductor memory device including an internal clock doubler including an internal clock doubler for doubling an external clock signal in a read mode to output a double clock signal in response to a plurality of external control signals, and delaying the external clock signal to |
| 7075845 |
FeRAM and sense amplifier array having data bus pull-down sensing function and sensing method us |
July 11, 2006 |
| A nonvolatile ferroelectric memory device features a data bus pull-down sensing function. The nonvolatile ferroelectric memory device having a data bus pull-down sensing function comprises a plurality of cell array blocks, a common data bus unit and a sense amplifier array unit. The |
| 7075833 |
Circuit for detecting negative word line voltage |
July 11, 2006 |
| The present invention discloses a circuit for detecting a negative word line voltage including a detecting unit for detecting a negative word line voltage in a detection node by using a plurality of loads coupled in series between a power supply terminal and a negative word line voltage |
| 7075824 |
NAND flash memory device |
July 11, 2006 |
| Disclosed is a NAND flash memory device which includes butting taps that are formed in such a manner that a poly layer and a silicide layer are connected to given points at the ends of a DSL and the SSL of a NAND flash memory device through a metal contact. The butting taps reduces the |
| 7075810 |
Nonvolatile ferroelectric memory device |
July 11, 2006 |
| A nonvolatile ferroelectric memory device transmits/receives data of a cell by using a main bitline of a cell array block as a data bus in a system on chip (SOC) having a hierarchical bitline structure, thereby reducing the chip size. In the nonvolatile ferroelectric memory device, w |
| 7074668 |
Capacitor of semiconductor device and method for forming the same |
July 11, 2006 |
| In a method for forming a capacitor for use in a semiconductor device, a nitride film for stopping etching, a first mold oxide film, an insulating film, deposited on a substrate are etched to expose the respective storage node contacts and thereby to form a plurality of contact holes |
| 7074661 |
Method for fabricating semiconductor device with use of partial gate recessing process |
July 11, 2006 |
| Disclosed is a method for fabricating a semiconductor device with a polymetal gate electrode formed by a partial gate recessing process. The method includes the steps of forming a gate structure including a gate dielectric layer, a polysilicon layer, a metal layer, an etch stop layer |
| 7072221 |
Flash memory device and method for driving the same |
July 4, 2006 |
| A flash memory device which can reduce the whole program or erase time and improve reliability by cycling, by storing a pulse width or a bias level for passing at least one bit of cells of a first page in a program or erase operation using an ISPP scheme, and using the stored pulse width |
| 7072216 |
Method for reading flash memory cell, NAND-type flash memory apparatus, and NOR-type flash memor |
July 4, 2006 |
| The present invention relates to a method of reading a flash memory cell, a NAND-type flash memory apparatus, and a NOR-type flash memory apparatus. According to the present invention, it is possible to improve the resolution capability and reduce the determination time by means of d |
| 7072203 |
Hybrid switch cell and memory device using the same |
July 4, 2006 |
| A nonvolatile memory device features a hybrid switch cell as a cross-point cell using a nonvolatile ferroelectric capacitor and a hybrid switch. The hybrid switch cell comprises a ferroelectric capacitor and a hybrid switch. The ferroelectric capacitor, located where a word line and a bi |
| 7071772 |
Differential amplifier |
July 4, 2006 |
| There is provided a differential amplifier including: an output terminal through which an output voltage is outputted in response to an input voltage; a first inverter-type input unit connected between a first node and a second node to receive the input voltage; a second inverter-type |
| 7071059 |
Method for forming recess gate of semiconductor device |
July 4, 2006 |
| A method for forming a recess gate of a semiconductor device is disclosed. The method for forming a recess gate of a semiconductor device comprises forming a polysilicon layer pattern covering a contact region on a semiconductor substrate, etching a predetermined thickness of the sem |
| 7068567 |
Data output controller in semiconductor memory device and control method thereof |
June 27, 2006 |
| A data output controller of a high-speed memory device and a method therefor. The data output controller includes a first section for detecting a unit delay multiple of an external clock signal based on the external clock signal and a delay circuit of the external clock signal, a sec |
| 7068561 |
Semiconductor memory device for controlling cell block with state machine |
June 27, 2006 |
| A semiconductor memory device for an effective data access operation includes a cell area having N+1 number of unit cell blocks, each including M number of word lines, for storing a data in a unit cell corresponding to an inputted address; N+1 number of unit controlling blocks having |
| 7068553 |
Row redundancy circuit |
June 27, 2006 |
| A row redundancy circuit includes a fuse box group array, a redundant row predecoder and a redundant sub-row decoder. The fuse box group array includes a plurality of fuse box groups to detect row addresses. The redundant row predecoder performs a logic operation on an output signal |
| 7068549 |
Circuit for generating data strobe signal in semiconductor device and method thereof |
June 27, 2006 |
| Provided is directed to a circuit for generating a DQS signal in a semiconductor memory device which includes: a DQS data generation unit for generating a DQS preamble signal and a DQS data, signals earlier than a CAS latency; a DQS output control signal generation unit for generating |
| 7068547 |
Internal voltage generating circuit in semiconductor memory device |
June 27, 2006 |
| An internal voltage generating circuit in a semiconductor memory device includes a comparing unit for comparing a voltage level of an internal voltage with that of a reference voltage, a pull-up driving unit for performing a pull-up operation for an output terminal in response to an |
| 7068529 |
Nonvolatile ferroelectric memory device |
June 27, 2006 |
| The disclosed nonvolatile ferroelectric memory device comprises: a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of platelines, respectively; a read control block configured to convert the data level voltage stored in the me |
| 7067425 |
Method of manufacturing flash memory device |
June 27, 2006 |
| A method of manufacturing a flash memory device includes the steps of forming a nitride film on an entire surface of a trench by means of an annealing process to prevent implanted ions for adjusting a threshold voltage from diffusing to a device isolation region, and forming a side w |
| 7067390 |
Method for forming isolation layer of semiconductor device |
June 27, 2006 |
| Disclosed is a method for forming an isolation layer of a semiconductor device. The method includes the steps of providing a semiconductor substrate having a predetermined isolation region, sequentially forming a pad oxide layer and a pad nitride layer exposing the predetermined isol |
| 7067389 |
Method for manufacturing semiconductor device |
June 27, 2006 |
| The present invention discloses a method for forming an element isolation film of a semiconductor device, comprising the steps of: sequentially forming a pad oxide film, a pad nitride film and a mask oxide film on a semiconductor substrate on which a first region for forming a high v |
| 7067369 |
Flash memory cell transistor and method for fabricating the same |
June 27, 2006 |
| A flash memory cell transistor and a method for fabricating the same compensates a work function difference of a pMOS and a nMOS with a triple gate insualting film by using electron density trapped in a pMOS gate insulating film. The flash memory cell transistor comprises a p-well re |
| 7067367 |
Method for reducing poly-depletion due to thickness variation in a polysilicon layer in dual gat |
June 27, 2006 |
| Disclosed is a method for reducing poly-depletion in a dual gate CMOS fabrication process. The method reduces the poly-depletion in a dual gate CMOS fabrication process by increasing the doping efficiency in a gate polysilicon film. In order to increase the doping efficiency, the method |
| 7064989 |
On-die termination control circuit and method of generating on-die termination control signal |
June 20, 2006 |
| Provided is directed to an on-die termination control circuit and a method for generating an on-die termination control signal, and the circuit and the method are capable of performing an optimized termination operation during data input and output, by generating a control signal during |
| 7064370 |
Method for manufacturing semiconductor device and the device thereof |
June 20, 2006 |
| The present invention relates to a method of manufacturing a semiconductor device. The method comprises the steps of forming a plurality of lower bit lines arranged in a first direction on a semiconductor substrate by performing ion implantation using a mask defining the lower bit lines, |
| 7061826 |
Command decoder of semiconductor memory device |
June 13, 2006 |
| A command decoder is provided for controlling internal circuits of a semiconductor chip to operate in synchronism with a first internal clock signal having a pulse width, which is twice as wide as that of an external clock signal, and a second internal clock signal having an opposite |
| 7061824 |
Address buffer circuit for memory device |
June 13, 2006 |
| Disclosed is an address buffer circuit for a memory device, the address buffer circuit comprising: a first address input buffer group and a second address input buffer group for receiving an address signal applied from the exterior; and a control unit for controlling operation of the |
| 7061813 |
Page buffer of non-volatile memory device and method of programming and reading non-volatile mem |
June 13, 2006 |
| A page buffer of a non-volatile memory device and a method for programming and reading the same is provided. The page buffer includes a first latch unit and one or more second latch units for storing data, transfer units connected between the first latch unit and the second latch units f |
| 7061287 |
Delay locked loop |
June 13, 2006 |
| Provided is a delay locked loop comprising: a delay unit for delaying a clock supplied from an external chipset by a predetermined delay amount; a replica for delaying the clock delayed in the delay unit by a delay amount of a clock path and a data path; and a phase detector for gene |
| 7061005 |
Phase-change random access memory device and method for manufacturing the same |
June 13, 2006 |
| Disclosed are a phase-change random access memory device and a method for manufacturing the same by performing a photolithography process using electronic beam. The phase-change random access memory device includes a first insulation layer having first contact holes and a second contact |
| 7060630 |
Method of forming isolation film of semiconductor device |
June 13, 2006 |
| Disclosed is a method of forming the isolation film in the semiconductor device. The method comprises the steps of sequentially forming a pad oxide film and a pad nitride film on a silicon substrate, forming a photoresist pattern through which an isolation region is opened, on the pa |
| 7060616 |
Method of manufacturing semiconductor device |
June 13, 2006 |
| The present invention is provided to manufacture a semiconductor device capable of preventing loss of dopants due to external diffusion thereof from a junction area by forming a cobalt mono-silicide film through a first RTP process, implanting ions not serving as a donor or an acceptor |
| 7060610 |
Method for forming contact in semiconductor device |
June 13, 2006 |
| The present invention relates to a method for forming a contact in a semiconductor device. The method includes the steps of: forming a P-type source/drain junction in a substrate; forming an inter-layer insulation layer on the substrate; forming a contact hole exposing at least one p |
| 7060577 |
Method for forming metal silicide layer in active area of semiconductor device |
June 13, 2006 |
| The present invention provides a method for forming a metal silicide layer in an active area of the semiconductor device. The method for forming the metal silicide layer includes: forming a source/drain junction area on a silicon substrate; forming an attack protection layer on the sourc |
| 7058756 |
Circuit for implementing special mode in packet-based semiconductor memory device |
June 6, 2006 |
| Disclosed is a circuit for implementing a special mode in a packet-based semiconductor memory device, which performs the special mode in the same manner as a normal operation without changing the semiconductor memory devie from a special mode register to a control register mode prior to |
| 7057970 |
Nonvolatile ferroelectric memory and control device using the same |
June 6, 2006 |
| A nonvolatile ferroelectric memory immediately outputs data stored in a page buffer without performing a cell access operation when a page buffer is accessed. Since a block page address region and a column page address region are arranged in less significant bit region, and a row address |
