| Patent Number |
Title Of Patent |
Date Issued |
| 7205814 |
Pulse generator |
April 17, 2007 |
| The disclosure is directed to an internal pulse generator outputting a signal with a constant pulse width nevertheless of a frequency of an input signal, including a first PMOS transistor, a PMOS second transistor and an NMOS transistor which are connected between a power supply voltage |
| 7205242 |
Method for forming isolation layer in semiconductor device |
April 17, 2007 |
| The present invention relates to a method for forming an insulating layer in a semiconductor device. After a first oxide film is formed in a trench, an impurity remaining on the first oxide film in the process of etching the first oxide film using a gas containing fluorine is stripped |
| 7205192 |
Semiconductor memory device capable of preventing oxidation of plug and method for fabricating t |
April 17, 2007 |
| A semiconductor device and a fabrication method thereof provides a plug structure composed of a diffusion barrier layer formed at the bottom and on the sides of a contact hole and an oxidation barrier layer formed on the diffusion barrier layer that fills up the inside of the contact hol |
| 7205089 |
Cross-linking polymer for organic anti-reflective coating, organic anti-reflective coating compo |
April 17, 2007 |
| A cross-linking polymer for an organic anti-reflective coating that is able to improve the uniformity of an ultra-fine photoresist pattern formed using a photolithography process and an ArF light source with 194 nm wavelength. Organic anti-reflective coatings including the same and a |
| 7202174 |
Method of forming micro pattern in semiconductor device |
April 10, 2007 |
| A method of forming a micro pattern in a semiconductor device, wherein a first polysilicon film, a buffer oxide film, a second polysilicon film, an anti-polishing film, and a first oxide film are sequentially laminated on a semiconductor substrate having a to-be-etched layer. The first o |
| 7202134 |
Method of forming transistors with ultra-short gate feature |
April 10, 2007 |
| A gate electrode is formed over but insulated from a semiconductor body region for each of first and second transistors. A DDD implant is carried out to from DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, off-set spacers are formed al |
| 7200044 |
Page buffer circuit with reduced size, and flash memory device having page buffer and program op |
April 3, 2007 |
| The present invention relates to a page buffer circuit with a reduced size, and a flash memory device having the page buffer circuit and program operation method thereof. According to the present invention, a page buffer circuit can perform a program operation of a Multi-Level Cell ( |
| 7200039 |
Flash memory device with improved erase function and method for controlling erase operation of t |
April 3, 2007 |
| The present patent relates to flash memory devices with improved erase function, and method of controlling an erase operation of the same. According to the present patent, the flash memory device includes memory cell blocks, each having a plurality of memory cells sharing local word |
| 7199053 |
Method for detecting end-point of chemical mechanical polishing process |
April 3, 2007 |
| Disclosed is a method for detecting an end-point of a CMP process of a semiconductor device. More specifically, when all polishing processes are performed using a nitride film as a polishing barrier film, a buffer layer including nitrogen is formed on the nitride film and a polishing |
| 7199051 |
Method for fabricating semiconductor device capable of preventing damages to conductive structur |
April 3, 2007 |
| Disclosed is a method for fabricating a semiconductor device with protected conductive structures. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask insulation layer fo |
| 7199043 |
Method of forming copper wiring in semiconductor device |
April 3, 2007 |
| Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing process to form a copper |
| 7199028 |
Method for manufacturing semiconductor device |
April 3, 2007 |
| Provided is a method for manufacturing a semiconductor device capable of preventing a solution from penetrating a lower layer by forming a poly silicon layer stacked of the films having the different grain boundary structures at border, wherein the solution is used in the subsequent |
| 7199004 |
Method of forming capacitor of semiconductor device |
April 3, 2007 |
| Disclosed is a method of forming a capacitor of a semiconductor device which can secure a desired leakage current characteristic while securing a desired charging capacitance. The inventive method of forming a capacitor of a semiconductor device comprises steps of: forming a bottom e |
| 7198887 |
Organic anti-reflective coating polymer, its preparation method and organic anti-reflective coat |
April 3, 2007 |
| Disclosed are an organic anti-reflective coating polymer having a structure represented by the following formula I, its preparation method and an organic anti-reflective coating composition with respect to an ultra-fine pattern formation process of the photoresist for photolithograph |
| 7198881 |
Photoresist composition for EUV and method for forming photoresist pattern using the same |
April 3, 2007 |
| The present invention relates to photoresist compositions for EUV and methods for forming photoresist patterns. More specifically, fine photoresist patterns: of less than 50 nm without collapse are formed with EUV (Extreme Ultraviolet) as an exposure light source by using a negative |
| 7196949 |
Semiconductor memory device with reduced skew on data line |
March 27, 2007 |
| A semiconductor memory device including: a plurality of read sense amplifiers for amplifying an output data of a memory cell; a plurality of read delay controllers for delaying an output data of the read sense amplifier by a predetermined time; a plurality of read latches for outputt |
| 7196939 |
Method for controlling precharge timing of memory device and apparatus thereof |
March 27, 2007 |
| A method for controlling a precharge timing of a memory device is disclosed. The method includes making timing of generation of a signal for determining a precharge timing in a normal operation and a signal for determining a precharge timing in a refresh operation different from each |
| 7196538 |
Data acceleration device and data transmission apparatus using the same |
March 27, 2007 |
| There is provided a data acceleration device comprising a pull-up driver for driving a pull-up in response to the signal level on a first node, a pull-down driver for driving a pull-down in response to the signal level on the first node, a first pull-up circuit for pull-up driving a seco |
| 7196373 |
NAND flash memory device and method of forming a well of a NAND flash memory device |
March 27, 2007 |
| Disclosed herein are a NAND flash memory device and a method of forming a well of the NAND flash memory device. Triple wells of a NAND flash memory device are formed within a cell region in plural. A cell block including flash memory cells is formed on the triple wells. Accordingly, duri |
| 7193926 |
Memory device for reducing leakage current |
March 20, 2007 |
| Disclosed is a memory device for reducing leakage current generated by a bridge between a word line and a bit line when the memory device is in a waiting mode. The memory device includes: N memory cell blocks each of which includes plurality of memory cell blocks, wherein N represents a |
| 7193925 |
Low power semiconductor memory device |
March 20, 2007 |
| A low power semiconductor memory device can reduce power consumption of the whole chip by activating a bit line sense amplifier and a sub word line driver for driving a selected memory cell array block. The low power semiconductor memory device comprises a plurality of memory cell array |
| 7193920 |
Semiconductor memory device |
March 20, 2007 |
| A semiconductor memory device generates a control signal for regulating a potential of an internal power voltage when an extended mode register is set to adjust an operating speed and a tWR (time to write recovery) of a chip. The semiconductor memory device comprises an extended mode reg |
| 7193911 |
Page buffer for preventing program fail in check board program of non-volatile memory device |
March 20, 2007 |
| A page buffer in which the value of data that have been latched in a register of a page buffer is not changed by slowly transmitting data to the register in a check board program operation of a NAND flash memory device. The page buffer includes a first register having a first input u |
| 7193906 |
Voltage regulating circuit and method of regulating voltage |
March 20, 2007 |
| Provided is concerned with a voltage regulation circuit and method of regulating the voltage, including a reference voltage generator for generating a reference voltage by dividing a core voltage of a semiconductor memory device, a controller for controlling the reference voltage gen |
| 7193897 |
NAND flash memory device capable of changing a block size |
March 20, 2007 |
| Disclosed herein is a NAND flash memory device capable of changing a block size. In NAND flash memory devices capable of changing a block size, each memory block is divided into two page groups. Each memory block includes two block switches to select each page group in response to an ext |
| 7193315 |
Test vehicle grid array package |
March 20, 2007 |
| A TV-BGA package comprises: a PCB having bonding fingers; an adhesive material being coated on an edge of the PCB; a sealing post being adhered on the adhesive material; a semiconductor testing chip having a plurality of bonding pads adhered on the PCB; a plurality of metal wires separat |
| 7192883 |
Method of manufacturing semiconductor device |
March 20, 2007 |
| The present invention relates to a method of manufacturing a semiconductor device. A minute pattern is formed using a hard mask film of a series of a nitride film as an etch mask. Before a hard mask film removal process is performed, the step of performing given etching using an oxide fi |
| 7192825 |
Semiconductor memory device and method for fabricating the same |
March 20, 2007 |
| The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of |
| 7190606 |
Test mode control device using nonvolatile ferroelectric memory |
March 13, 2007 |
| A test mode control device using a nonvolatile ferroelectric memory enables a precise test of characteristics of a memory cell array by changing a reference voltage and timing regulated for a memory cell test in a software system without extra processes. In an embodiment, test modes |
| 7190203 |
Memory device having a duty ratio corrector |
March 13, 2007 |
| A memory device having a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an |
| 7189622 |
Method for fabricating semiconductor device |
March 13, 2007 |
| A method for fabricating a semiconductor device is disclosed. The method provides etching a predetermined region of a semiconductor substrate prior to formation of a device isolation film defining an active region and forming a gate having a stepped gate channel. |
| 7189618 |
Method of manufacturing a transistor of a semiconductor device |
March 13, 2007 |
| Disclosed are a semiconductor device and a method of manufacturing the same. According to the present invention, the transistor of the semiconductor device comprises a stack type gate in which a tunnel oxide film, a floating gate, a dielectric film and a control gate are sequentially |
| 7189605 |
Method for fabricating semiconductor device |
March 13, 2007 |
| Disclosed herein is a method for fabricating a memory device. According to the present invention, a device isolation film is etched using a mask partially exposing a channel region and the device isolation film adjacent thereto during the etching process of the recess gate region, an |
| 7189597 |
Semiconductor device and method for fabricating the same |
March 13, 2007 |
| The present invention relates to a semiconductor device with an improved contact margin between an interconnection line and a bit line and a method for fabricating the same. The semiconductor device includes: a bit line structure formed on a substrate and having a number of bit lines and |
| 7187584 |
Method of reading multi-level NAND flash memory cell and circuit for the same |
March 6, 2007 |
| The disclosed is a method of reading a multi-level NAND flash memory cell and a circuit for the same. The read circuit for the NAND flash memory device includes a NAND flash memory cell having multi-level information, a first page buffer for storing an upper-bit, a second page buffer for |
| 7187195 |
Parallel compression test circuit of memory device |
March 6, 2007 |
| A parallel compression test circuit of a memory device disperses peak current and reduce noise by operating input/output amplifiers at different timings in a parallel compression test mode. The parallel compression test circuit comprises an input/output amplification control unit for |
| 7186655 |
Method for manufacturing semiconductor device |
March 6, 2007 |
| The disclosure relates to a method for manufacturing a semiconductor device by performing a planarization process including a first CMP process using a slurry including 0.05.about.0.5 wt % CeO2 or MnO2 as an abrasive and a second CMP process using a slurry including SiO2 as the other |
| 7186647 |
Method for fabricating semiconductor device having landing plug contact structure |
March 6, 2007 |
| The present invention relates to a method for fabricating a semiconductor device with a landing plug contact structure. The method includes the steps of: forming a plurality of gate structures on a substrate; sequentially forming a first spacer and a second spacer on sidewalls of eac |
| 7186631 |
Method for manufacturing a semiconductor device |
March 6, 2007 |
| Provided is a method for manufacturing a semiconductor device comprising forming a device isolation layer on a semiconductor substrate; forming gate insulating layers on the upper part of the semiconductor substrate having the device isolation layers formed thereon; forming an undoped |
| 7186627 |
Method for forming device isolation film of semiconductor device |
March 6, 2007 |
| A method for forming device isolation film of semiconductor device is provided, the method including forming a pad oxide film, a pad nitride film, and an oxide film for device isolation on a semiconductor substrate, etching a predetermined region of the oxide film for device isolatio |
| 7186496 |
Light absorbent agent polymer useful for organic anti-reflective coating, its preparation method |
March 6, 2007 |
| Disclosed are a light absorbent agent polymer for organic anti-reflective coating which can prevent diffused light reflection of the bottom film layer or substrate and reduce standing waves caused by variation of thickness of the photoresist itself, thereby, increasing uniformity of |
| 7184912 |
Memory device with apparatus for recalibrating output signal of internal circuit and method ther |
February 27, 2007 |
| A memory device with an apparatus for recalibrating an output signal of an internal circuit is disclosed. The memory device includes a plurality of signal modulators for simultaneously receiving the output signal of the internal circuit, and a control unit for outputting a control signal |
| 7184362 |
Page access circuit of semiconductor memory device |
February 27, 2007 |
| A page access circuit of a semiconductor memory device is normally operated even when a page address toggles at any timing in a page mode. The page access circuit comprises an address buffer, a column control unit, a page control unit, a pre-active unit and a precharge unit. The colu |
| 7184357 |
Decoding circuit for memory device |
February 27, 2007 |
| Provided is a decoding circuit for a memory device which is improved in an operation of chip so as to enable the operation to be predictable by making a decoded result corresponding to an undefined code get a specific value. The decoding circuit for a memory device generates address sign |
| 7184355 |
Memory bank structure |
February 27, 2007 |
| The present invention relates to a memory bank structure. The memory bank structure includes: a plurality of sub-banks identified by a predetermined additional address; a plurality of local input/output line precharge units for precharging local input/output lines included in each of |
| 7184354 |
Memory device reduced power consumption in power down mode |
February 27, 2007 |
| A memory device capable of reducing power consumption when the operation mode is a deep power down mode, includes an external power source voltage line through which an external power source voltage is supplied; an internal voltage line through which an internal voltage generated in an |
| 7184342 |
Semiconductor memory device having enhanced sense amplifier |
February 27, 2007 |
| Disclosed is a semiconductor memory device with a reduced write recovery time and an increased refresh period. The semiconductor memory device incorporating a plurality of memory cells therein, including: a bit line sense amplifier (BLSA) array provided with a plurality of bit line sense |
| 7184331 |
Redundancy fuse control circuit and semiconductor memory device having the same and redundancy p |
February 27, 2007 |
| A semiconductor memory device including a fuse control circuit for providing with a plurality of fail word line addresses written in its own circuit in advance and outputting a redundancy signal representing that an input address is the same as one of the fail word line addresses, and |
| 7184325 |
Input circuit for memory device |
February 27, 2007 |
| An input circuit for a semiconductor memory device is disclosed. The input circuit controlling transmission paths for data having passed through a data input buffer by using a 1-clock shifted block column address is provided. In particular, a data input apparatus improving a data pro |
| 7184310 |
Sequential program-verify method with result buffering |
February 27, 2007 |
| A sequential program-verify method is used in a non-volatile memory device including a plurality of memory cells each one for storing a logic value, the cells being arranged into a plurality of alignments. The method includes the steps of: writing a set of target values into a plurality |
