| Patent Number |
Title Of Patent |
Date Issued |
| 7244650 |
Transistor and method for manufacturing the same |
July 17, 2007 |
| A transistor including a semiconductor substrate defined with an active region and a device isolation region, a gate formed on the semiconductor substrate, an insulating spacers formed on respective side walls of the gate, and source/drain junctions formed in the semiconductor substrate |
| 7242636 |
Clock control circuit and semiconductor memory device including the same and input operation met |
July 10, 2007 |
| The present invention relates to a clock control circuit that can reduce power consumption in the input operation of an address signal and control signals and semiconductor memory device including the same, and an input operation method of the semiconductor memory device. The clock contr |
| 7242075 |
Silicon wafers and method of fabricating the same |
July 10, 2007 |
| By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the |
| 7239561 |
Data I/O circuit of flash memory device with improved data I/O speed structure |
July 3, 2007 |
| A data I/O circuit of a flash memory device includes a page buffer connected to at least one pair of bit lines, a page buffer select circuit arranged to output complementary input data, which is received through a pair of I/O lines, to the page buffer, or outputs complementary sensing |
| 7238653 |
Cleaning solution for photoresist and method for forming pattern using the same |
July 3, 2007 |
| Cleaning solutions for photoresist are disclosed which are useful for cleaning a semiconductor substrate in the last step of development when photoresist patterns are formed. Also, methods for forming photoresist patterns using the same are disclosed. The disclosed cleaning solution |
| 7238574 |
Flash memory device and method of manufacturing the same |
July 3, 2007 |
| A non-volatile memory device has a gate dielectric film formed between a floating gate and a control gate. The gate dielectric film is formed by forming an oxide film and a ZrO.sub.2/Al.sub.2O.sub.3/ZrO.sub.2 (ZAZ) film. Accordingly, the reliability of non-volatile memory devices can be |
| 7236397 |
Redundancy circuit for NAND flash memory device |
June 26, 2007 |
| A redundancy circuit for a NAND flash memory device reduces a test time and production time of the device, by performing a redundancy operation through a repair select unit using a cam cell. In addition, the redundancy circuit employs a repair method using a redundancy cam which can |
| 7235458 |
Method of forming an element isolation film of a semiconductor device |
June 26, 2007 |
| Disclosed herein is a method of forming an element isolation film of a semiconductor device. An aluminum oxide film of a high wet etch rate is used as a pad oxide film, a trench is formed, and top and bottom edges of the trench is made rounded while removing some of the aluminum oxide fi |
| 7235452 |
Method for fabricating capacitor in semiconductor device |
June 26, 2007 |
| A method for fabricating a capacitor in a semiconductor device is disclosed. The method comprises the steps of: forming an interlayer insulating film on a semiconductor substrate, which includes a first contact hole exposing a certain portion of the substrate; forming a storage node |
| 7235449 |
Method of forming a gate oxide film for a high voltage region of a flash memory device |
June 26, 2007 |
| A method of forming a gate oxide film for high voltage region of semiconductor devices includes forming patterns on a semiconductor substrate having a high voltage region, thereby exposing only a gate oxide film formation region for high voltage, forming a metal oxidization layer on |
| 7235349 |
Process for forming an ultra fine pattern using a bottom anti-reflective coating film containing |
June 26, 2007 |
| A process of forming ultra fine patterns using bottom anti-reflective coating containing acid generator. More particularly, a process of forming vertical patterns using an organic bottom anti-reflective coating containing excessive amount of acid generator, in order to prevent format |
| 7233533 |
Method for controlling data output timing of memory device and device therefor |
June 19, 2007 |
| Disclosed is a device for controlling data output of a memory device using a DLL clock signal, the device comprising: an output driver for outputting data; and a CAS latency control unit for generating a signal adjusting an operation timing of the output driver depending on CAS laten |
| 7233213 |
Oscillator of semiconductor device |
June 19, 2007 |
| An oscillator of a semiconductor memory device, wherein a reference voltage that flexibly shifts according to the shift in a power supply voltage is generated, and a reference clock is generated using the reference voltage. It is thus possible to generate the reference clock having a |
| 7233193 |
High voltage switching circuit of a NAND type flash memory device |
June 19, 2007 |
| A high voltage switching circuit of a NAND type flash memory device that includes a clock level shifter for increasing an amplitude of a clock signal, a pass voltage generator for outputting a pass voltage by pumping a power source voltage in response to a clock signal with an increased |
| 7231472 |
Input/output byte control device using nonvolatile ferroelectric register |
June 12, 2007 |
| An input/output byte control device using a nonvolatile ferroelectric register can maintain compatibility with various memories by selectively controlling bytes of input/output data. Since bytes of input/output data are selectively activated, the compatibility can be maintained with SRAM |
| 7230875 |
Delay locked loop for use in synchronous dynamic random access memory |
June 12, 2007 |
| A delay locked loop (DLL) for compensating for a skew in a synchronous dynamic random access memory includes: a delay model means for delaying an external clock signal by the skew to generate a delayed clock signal; a control unit, in response to the external clock signal and the delayed |
| 7230860 |
Voltage pumping device |
June 12, 2007 |
| A voltage pumping device is disclosed. The device comprises a reference voltage generator for generating a reference voltage having different levels depending on whether a semiconductor device is in a self-refresh mode or not, a voltage level detector for outputting a voltage pumping |
| 7229912 |
Method for forming passivation film of semiconductor device and structure of passivation film of |
June 12, 2007 |
| Disclosed are a method of manufacturing a semiconductor device and a structure of a semiconductor device. A method of forming a passivation film of a semiconductor device comprises the steps of forming metal wires on a semiconductor substrate, forming a buffer oxide film being a first |
| 7229904 |
Method for forming landing plug contacts in semiconductor device |
June 12, 2007 |
| Disclosed is a method for forming landing plug contacts in a semiconductor device. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer on the gate structures; |
| 7229888 |
Capacitor with hafnium oxide and aluminum oxide alloyed dielectric layer and method for fabricat |
June 12, 2007 |
| The present invention relates to a capacitor having a hafnium oxide and aluminum oxide alloyed dielectric layer and a method for fabricating the same. The capacitor includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the die |
| 7228370 |
Data output device and method of semiconductor device |
June 5, 2007 |
| A data output device is disclosed having a first comparator for comparing first output data with arbitrary output data on a bit-by-bit basis and outputting a first pre-flag signal, a second comparator for comparing second output data with the first output data on a bit-by-bit basis and |
| 7227811 |
Address latch signal generation circuit and address decoding circuit |
June 5, 2007 |
| An address latch signal generation circuit and an address decoding circuit may generate an address latch signal capable of latching pre-decoded internal address signals. The circuits may include a plurality of address transition detectors, each of the address transition detectors receivi |
| 7227794 |
Internal voltage generation control circuit and internal voltage generation circuit using the sa |
June 5, 2007 |
| Disclosed herein are an internal voltage generation control circuit and an internal voltage generation circuit using the same. The internal voltage generation control circuit comprises a row active controller for enabling a first internal voltage generation control signal when a row acti |
| 7227403 |
Internal voltage generator for semiconductor device |
June 5, 2007 |
| Disclosed is an internal voltage generator, which includes a detecting means for detecting a level of an internal voltage, an oscillator for generating a driving pulse signal in response to an output signal of the detecting means, a first driving unit for outputting a first pulse signal |
| 7227269 |
Wiring structure for a pad section in a semiconductor device |
June 5, 2007 |
| The wiring structure of a pad section in a semiconductor device includes a row of pads and a plurality of first bias wirings provided at either side of the row of pads on a same plane. The first bias wirings carry electrical signals to the pads. A plurality of second bias wirings is |
| 7227210 |
Ferroelectric memory transistor with highly-oriented film on gate insulator |
June 5, 2007 |
| A method for fabricating a non-volatile memory device. The method includes providing a substrate, e.g., silicon. The method also includes forming an oxide layer overlying the substrate; and forming a buffer layer overlying the oxide layer. A ferroelectric material is formed overlying the |
| 7227199 |
Image sensor and method of manufacturing the same |
June 5, 2007 |
| Disclosed is a method of manufacturing an image sensor having light sensitivity over a photodiode equal in area to that of a unit pixel. The image sensor includes an image sensor comprising: a first semiconductor substrate doped with a first conductive dopant; a first diffusion layer |
| 7226829 |
Method for fabricating semiconductor device |
June 5, 2007 |
| The present invention is related to a method for forming a storage node of a semiconductor device. The method includes the steps of: (a) forming a plurality of bit line patterns, each including a wire and a hard mask sequentially stacked on a surface of a substrate structure; (b) seq |
| 7226814 |
Semiconductor package device and method for fabricating the same |
June 5, 2007 |
| Disclosed are a semiconductor package device and a method for fabricating the semiconductor package device. The semiconductor package has a semiconductor chip including a plurality of bonding pads having a microscopic size and aligned at a minute interval, a planar layer formed on th |
| 7224194 |
Output driver circuit |
May 29, 2007 |
| The present invention relates to an output driver circuit which exhibits a reduced variation in the slew rate of an output signal thereof, irrespective of a variation in temperature occurring during a process carried out by a semiconductor memory device, to which the output driver ci |
| 7224179 |
Apparatus for adjusting slew rate in semiconductor memory device and method therefor |
May 29, 2007 |
| The present invention relates to an apparatus for adjusting a slew rate of a data signal outputted by a signal from an external circuit in a semiconductor memory device and a method therefor. The apparatus includes: a slew rate control signal generation block for outputting a plurali |
| 7223661 |
Method of manufacturing semiconductor device |
May 29, 2007 |
| The method includes forming an isolation film on a silicon substrate to define an active region; forming an antireflective film on an entire surface of the substrate containing the isolation film; forming a photosensitive film pattern on the antireflective film while exposing a porti |
| 7223655 |
Method for manufacturing NAND flash device |
May 29, 2007 |
| Disclosed is a method for manufacturing a NAND flash device. After a source line plug hole is formed, a drain contact plug hole is formed. The holes are filled with a conductive material film and are then polished. It is therefore possible to simplify the process since a blanket etch |
| 7221598 |
Method of controlling program operation of flash memory device with reduced program time |
May 22, 2007 |
| A method of controlling a program operation of a flash memory device includes performing a first program process of programming lower bit program data into MLCs of a selected page, a second program process of programming upper bit program data into the MLCs of the selected page, a fi |
| 7221573 |
Voltage up converter |
May 22, 2007 |
| The present invention discloses a voltage up converter, including: a detector for detecting a level of an internal power to generate the internal power higher than an external power; an asymmetrical oscillator for generating a frequency in which a high level width and a low level wid |
| 7220679 |
Method for forming patterns in a semiconductor device |
May 22, 2007 |
| A method for forming a pattern of a semiconductor device is disclosed which can increase the contact area between a photoresist and an anti-reflective film by performing an etching process on the anti-reflective film in a process of forming a photoresist pattern for a semiconductor d |
| 7215594 |
Address latch circuit of memory device |
May 8, 2007 |
| An address latch circuit of a memory device is disclosed. A latch operation is disabled while an address signal makes a level transition in the memory device, and then enabled when the address signal is stabilized after the level transition. Therefore, it is possible to reduce power |
| 7215588 |
Apparatus for controlling self-refresh period in memory device |
May 8, 2007 |
| Disclosed is an apparatus for controlling a self-refresh period in a memory device capable of normally performing a self-refresh operation that is indispensable to the operation of a volatile memory device using a refresh period control even if the inner temperature of the memory dev |
| 7214584 |
Method for forming semiconductor device capable of preventing bunker defect |
May 8, 2007 |
| Disclosed is a method for preventing a bunker defect generation on a lower portion of a cylinder type metal bottom electrode. The method includes the steps of: forming an etch stop layer on a bottom structure with a conductive region and an insulation region; forming a capacitor insu |
| 7213100 |
Method and apparatus for masking postamble ringing phenomenon in DDR SDRAM |
May 1, 2007 |
| A method for apparatus for masking a postamble ringing phenomenon in a DDR SDRAM comprising the steps of storing data, which are applied from a memory controller, in a data input latch through a data buffer and aligning the stored data, controlling the data input latch in such a mann |
| 7212451 |
Column selection signal generator of semiconductor memory device |
May 1, 2007 |
| A column selection signal generator of a semiconductor memory device is configured to maintain a predetermined pulse width of a column selection signal regardless of change in process and external conditions by selectively using a self-generated pulse signal and a pulse signal genera |
| 7212450 |
FeRAM having differential data |
May 1, 2007 |
| Disclosed is a non-volatile ferroelectric memory device having differential data, the device including: a plurality of cell array block groups having a hierarchy bit line structure and storing differential data; a common data bus being shared by a plurality of the cell array block gr |
| 7212439 |
NAND flash memory device and method of programming the same |
May 1, 2007 |
| Provided is directed to a NAND flash memory device and a method of programming the same, which can improve integration of the device by removing a common source line connecting with a source line coupled to a plurality of cell blocks, control a voltage applied to a source line by eac |
| 7212431 |
Nonvolatile ferroelectric memory device and control method thereof |
May 1, 2007 |
| A nonvolatile ferroelectric memory device and a control method thereof are provided to control read/write operations of memory cell arrays whose channel resistance is differentiated depending on a polarity state of a ferroelectric material. In the device, data read from a memory cell are |
| 7212429 |
Nonvolatile ferroelectric memory device |
May 1, 2007 |
| A nonvolatile ferroelectric memory device comprises a cell array block, a sense amplifier unit, a main amplifier unit and a data bus unit. The ferroelectric sense amplifier effectively senses and amplifies cell data having a small voltage difference applied to a main bit line, thereby |
| 7212428 |
FeRAM having differential data |
May 1, 2007 |
| A non-volatile ferroelectric memory device having differential datacomprises a plurality of cell array blocks and a data buffer unit. Each of the plurality of cell array blocks includes cell arrays and sense amplifiers. The cell array has a hierarchical bit line architecture and are |
| 7211524 |
Method of forming insulating layer in semiconductor device |
May 1, 2007 |
| The present invention relates to a method of forming an insulating film in a semiconductor device. After a mixed gas of alkyl silane gas and N.sub.2O gas is supplied into the deposition equipment, a radio frequency power including a short pulse wave for causing incomplete reaction upon a |
| 7211488 |
Method of forming inter-dielectric layer in semiconductor device |
May 1, 2007 |
| The present invention relates to a method of forming an interlayer dielectric film in a semiconductor device. More particularly, the present invention selectively forms an insulating film spacer only at a region where a plug is formed between metal lines and removes the insulating fi |
| 7211484 |
Method of manufacturing flash memory device |
May 1, 2007 |
| Disclosed is a method of manufacturing a flash memory device. In a flash memory device using a SA-STI scheme, a trench for isolation is buried with oxide. A field oxide film is then formed by means of a polishing process. Next, field oxide films of a cell region and a low-voltage tra |
| 7209393 |
Semiconductor memory device and method for multiplexing write data thereof |
April 24, 2007 |
| A semiconductor memory device including a write multiplexer unit that multiplexes write data transmitted to a global I/O bus disposed in front of a write driver. The semiconductor memory device further includes a memory core region including an array of memory cells, a data input path |
