| Patent Number |
Title Of Patent |
Date Issued |
| RE40172 |
Multi-bank testing apparatus for a synchronous dram |
March 25, 2008 |
| A multi-bank testing apparatus for a synchronous DRAM, which allows all banks of the synchronous DRAM to simultaneously carry out their write and read operations in a test mode, thereby being capable of testing the entire bank in order to reduce the test time being likely to increase in |
| RE40076 |
Program circuit |
February 19, 2008 |
| The program circuit according to the present invention can apply a program voltage to the only memory cells which are not programmed during a re-programming operation, thus, the present invention can be prevent a lowering of reliability of the memory cell due to a continued supply of a |
| 7619946 |
Active driver for use in semiconductor device |
November 17, 2009 |
| An active driver includes an internal voltage supply node, an internal voltage generator, and a test internal voltage driving circuit. The internal voltage generator generates an internal voltage having a first potential level in a normal operation to provide the internal voltage to |
| 7619943 |
Circuit and method for controlling self-refresh cycle |
November 17, 2009 |
| The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh cycle can be variably controlled. Detectors each detecting whether or not a voltage charged |
| 7619942 |
Multi-port memory device having self-refresh mode |
November 17, 2009 |
| The multi-port memory device includes a mode input/output controller for receiving a flag signal and generating a self-refresh entry signal and a self-refresh escape signal, a refresh interval signal generator for providing a self-refresh interval signal notifying a self-refresh inte |
| 7619940 |
Apparatus and method of generating power up signal of semiconductor integrated circuit |
November 17, 2009 |
| An apparatus for generating a power up signal for a semiconductor memory chip includes a temperature information providing unit that outputs a control voltage corresponding to predetermined temperature information. A power up signal generating unit generates the power up signal based at |
| 7619937 |
Semiconductor memory device with reset during a test mode |
November 17, 2009 |
| A semiconductor memory device performs a reset operation at a wafer state by using a signal input through an address pin in a test mode. The semiconductor memory device includes a buffer for transferring a reset command in response to a reset-active signal and a test reset signal, a |
| 7619927 |
Non-volatile memory device and method for fabricating the same |
November 17, 2009 |
| A non-volatile memory device includes a plurality of memory cells coupled in series, a plurality of word lines coupled to the respective memory cells, and a plurality of spacers interposed between the word lines and having different dielectric constants according to line widths of the |
| 7619454 |
Clock generator for semiconductor memory apparatus |
November 17, 2009 |
| The clock generator for semiconductor memory apparatus which includes: a first divider configured to divide a frequency of a first internal clock generated by using an external clock; a first delay unit configured to delay an output of the first divider by first delay time; a second |
| 7618885 |
Semiconductor device having a recess channel and method for fabricating the same |
November 17, 2009 |
| Provided is a semiconductor device having recess channel, comprising a semiconductor substrate having first and second trenches disposed to cross each other on both sides of an active region among adjoining regions between an active region and element-isolation films; a gate insulati |
| 7618860 |
Method for fabricating semiconductor device |
November 17, 2009 |
| A method for fabricating a semiconductor device includes forming a first insulating layer over a substrate where a landing contact plug is formed, forming an etch barrier pattern having a line type open region over the first insulating layer, forming a second insulating layer for pla |
| 7616630 |
Semiconductor memory device |
November 10, 2009 |
| A semiconductor memory device resolves skew problem due to delay difference between the case when data that is inputted through data input/output (IO) pin is transferred to one global I/O bus and the case when transferred to another global I/O bus based on data width option. The semi |
| 7616521 |
Semiconductor memory device selectively enabling address buffer according to data output |
November 10, 2009 |
| A semiconductor memory device can reduce needless current consumption when addresses are inputted. A semiconductor memory device includes a clock enable buffering unit for receiving a clock enable signal to output a buffer enable signal, an address buffer control unit for generating an |
| 7616518 |
Multi-port memory device with serial input/output interface |
November 10, 2009 |
| A multi-port memory device includes a plurality of ports located at a center region of the multi-port memory device, each for performing a data communication with a corresponding external device; a plurality of banks arranged at upper and lower regions of the multi-port memory device in |
| 7616511 |
Input/output line sense amplifier and semiconductor memory device using the same |
November 10, 2009 |
| An input/output (I/O) line sense amplifier includes a buffer unit, a sense amplifier, and a precharge unit. The buffer unit is driven by a first level voltage to buffer a strobe signal, and the sense amplifier is driven by a second level voltage to amplify a signal of an I/O line in |
| 7616496 |
Charge trap type non-volatile memory device and program method thereof |
November 10, 2009 |
| A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device |
| 7616486 |
Cell array of semiconductor memory device and method of driving the same |
November 10, 2009 |
| A cell array of a flash memory device includes first and second memory block units, and a voltage generator. Each of the first and second memory block units includes a plurality of memory blocks having a plurality of memory cells. The voltage generator outputs a source voltage, a power |
| 7616426 |
Capacitor and method for fabricating the same |
November 10, 2009 |
| A capacitor includes a lower electrode, a dielectric structure over the lower electrode, the dielectric structure including at least one crystallized zirconium oxide (ZrO.sub.2) layer and at least one amorphous aluminum oxide (Al.sub.2O.sub.3) layer, and an upper electrode formed ove |
| 7616415 |
Electrostatic discharge protection circuit and electrostatic discharge protection method of a se |
November 10, 2009 |
| An electrostatic discharge (ESD) protection circuit protects a gate oxide of elements in an internal circuit against ESD. During an ESD test, if the sum of driving voltages of ESD protectors connected between a power pad and a ground pad is higher than the gate oxide breakdown voltage of |
| 7616049 |
Pumping voltage generating apparatus of semiconductor integrated circuit |
November 10, 2009 |
| A pumping voltage generating apparatus includes a detection signal generating unit that generates a detection signal when a pumping voltage is lower than a reference value. A pumping unit elevates a first external voltage by a second external voltage to be output as the pumping voltage, |
| 7616038 |
Clock modulation circuit for correcting duty ratio and spread spectrum clock generator including |
November 10, 2009 |
| A clock modulation circuit includes a modulation block that receives a fixed clock generated from a reference clock and buffers the fixed clock so as to generate a modulated clock. A correction unit is provided in the modulation block to correct the duty ratio of the modulated clock. |
| 7616034 |
Circuit for controlling data output |
November 10, 2009 |
| Disclosed is a data output control circuit for controlling data output. The data output control circuit includes a delay lock loop for outputting a first clock by delaying an external clock in response to a control signal, a phase detector for outputting a detection signal by detecting a |
| 7616032 |
Internal voltage initializing circuit for use in semiconductor memory device and driving method |
November 10, 2009 |
| Provided are an internal voltage initializing circuit for use in a semiconductor memory and a driving method thereof, which are capable of preventing a back bias voltage from abnormally increasing due to a pumping operation of a VPP pump according to a change in a level of a power-up |
| 7616030 |
Semiconductor device and operation method thereof |
November 10, 2009 |
| Semiconductor device and operation method thereof includes an aspect of the present invention, there is provided a clock generator configured to receive an external clock signal to generate a first clock signal corresponding to a rising edge of the external clock and a second clock s |
| 7616022 |
Circuit and method for detecting skew of transistors in a semiconductor device |
November 10, 2009 |
| A circuit and method for easily detecting skew of a transistor within a semiconductor device are provided. The circuit for detecting the skew of the transistor includes a linear voltage generating unit for outputting a linear voltage by using a first supply voltage, a first attenuation u |
| 7615843 |
Guard ring device receiving different voltages for forming decoupling capacitor and semiconducto |
November 10, 2009 |
| A semiconductor device in which a decoupling capacitor is formed by supplying different power levels to a guard ring device is disclosed. The semiconductor device includes a guard ring, having conductive rings, which surrounds a memory chip. The conductive rings are stacked in a mult |
| 7615769 |
Nonvolatile memory device and fabrication method thereof |
November 10, 2009 |
| A nonvolatile memory device and a method for its fabrication may ensure uniform operating characteristics of ReRAM. The ReRam may include a laminated resistance layer that determines phase of ReRAM on an upper edge of a lower electrode for obtaining a stable threshold drive voltage l |
| 7615497 |
Forming fine pattern of semiconductor device using three mask layers and CMP of spin-on carbon l |
November 10, 2009 |
| A method for forming a fine pattern of a semiconductor device includes forming a deposition film over a substrate having an underlying layer. The deposition film includes first, second, and third mask films. The method also includes forming a photoresist pattern over the third mask f |
| 7615494 |
Method for fabricating semiconductor device including plug |
November 10, 2009 |
| A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, etching the insulation layer using a hard mask pattern to form a contact hole, filling the contact hole with a conductive layer, etching the conductive layer to form a plug in the c |
| 7615493 |
Method for forming alignment mark |
November 10, 2009 |
| A method for forming an alignment mark comprises forming an etch stop film and an interlayer insulating film over a semiconductor substrate including a cell region and a scribe region, etching a predetermined region of the interlayer insulating film and the etch stop film to form a s |
| 7615490 |
Method for fabricating landing plug of semiconductor device |
November 10, 2009 |
| A method of fabricating a landing plug of a semiconductor device includes performing a double patterning process to separately form a landing plug contact hole for a storage node and a landing plug contact hole for a bit line, thereby facilitating forming a device having a half pitch of |
| 7615478 |
Fabrication method for electronic system modules |
November 10, 2009 |
| This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid |
| 7615461 |
Method for forming shallow trench isolation of semiconductor device |
November 10, 2009 |
| A method for forming a shallow trench isolation (STI) of a semiconductor device comprises forming a nitride film pattern over a semiconductor substrate having a defined lower structure, etching a predetermined thickness of the semiconductor substrate using the nitride film pattern as |
| 7615451 |
Method for forming semiconductor device |
November 10, 2009 |
| A method for forming a semiconductor device is provided. More specifically, a method for forming a bulb-shaped portion of a bulb-shaped recess gate is provided to overcome an etching process margin reduction caused by a spacer oxide film formed on sidewalls of a recess and thickly la |
| 7615450 |
Method of manufacturing flash memory device |
November 10, 2009 |
| Disclosed herein is a method of fabricating a flash memory device. The method includes providing a semiconductor substrate that includes an active region and a field region. A tunnel insulating layer and a first conductive layer are formed in the active region, and an isolation struc |
| 7615449 |
Semiconductor device having a recess channel transistor |
November 10, 2009 |
| The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof and a recess channel region formed in the semiconductor substrate |
| 7615338 |
Photoresist coating composition and method for forming fine pattern using the same |
November 10, 2009 |
| A photoresist coating composition that includes a compound represented by Formula 1 and an aqueous solvent, and a method for forming a fine pattern by coating the composition on a photoresist pattern to effectively reduce a size of a photoresist contact hole and a space, which can be app |
| 7613069 |
Address latch circuit of semiconductor memory device |
November 3, 2009 |
| An address latch circuit of a semiconductor memory device is provided. The address latch circuit includes a first address latch part, which latches a first address signal fed from outside according to a first address latch signal and outputs a second address signal. An address shift part |
| 7613065 |
Multi-port memory device |
November 3, 2009 |
| In a multi-port memory device, a plurality of ports simultaneously access a plurality of banks through global data buses. A data conflict detector compares valid data signals input from the plurality of ports through the global data buses to the plurality of banks, and detects data confl |
| 7613059 |
Semiconductor memory device and method for driving the same |
November 3, 2009 |
| A semiconductor memory device can stabilize a voltage level of a normal driving voltage terminal in a normal driving operation, which is performed after an overdriving operation, even when an overdriving voltage is unstable due to environmental factors of the semiconductor memory dev |
| 7612596 |
Internal clock generator |
November 3, 2009 |
| An internal clock generator that modulates a high-frequency clock signal to a low-frequency signal to transmit the low-frequency signal if a transmission line for transmitting the high-frequency clock signal is long, and then restores the transmitted low-frequency signal to the high- |
| 7612593 |
Duty detection circuit |
November 3, 2009 |
| Semiconductor memory device with duty correction circuit includes a clock edge detector configured to generate first and second detection pulses in response to a transition timing of a common clock signal in an initial measurement operation; a duty detector configured to compare the firs |
| 7612591 |
DLL circuit of semiconductor memory apparatus and method of delaying and locking clock in semico |
November 3, 2009 |
| A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock by a predetermined valu |
| 7611964 |
Method of forming isolation layer of semiconductor memory device |
November 3, 2009 |
| The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge trap layer are formed |
| 7611946 |
Method of fabricating a non-volatile memory device |
November 3, 2009 |
| A method of fabricating a non-volatile memory device prevents the threshold voltage of a program-inhibited cell from rising by preventing hot carriers, generated in a semiconductor substrate near a select line, from being injected into a floating gate of the program-inhibited cell. T |
| 7610165 |
Semiconductor memory device having on die thermal sensor |
October 27, 2009 |
| A semiconductor memory device includes: a temperature information output unit for measuring an internal temperature of the semiconductor memory device, and generating a plurality of flag signals, each voltage level of which varies according to the measured internal temperature; a sel |
| 7609801 |
Counter circuit and method of operating the same |
October 27, 2009 |
| A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the pl |
| 7609800 |
Counter of semiconductor device |
October 27, 2009 |
| The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in synchronism with a clock signal. The second MUX |
| 7609566 |
Semiconductor memory device |
October 27, 2009 |
| A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping operation to an external power in order to generate an internal voltage having a level lower than |
| 7609548 |
Method of programming a multi level cell |
October 27, 2009 |
| The present invention relates to a method of programming a multi level cell capable of storing above 1 data bit. The method includes storing first data in a first storing unit, storing second data in a second storing unit, programming a least significant bit data in accordance with t |
