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Hynix Semiconductor Inc. Patents
Assignee:
Hynix Semiconductor Inc.
Address:
Icheon-si, KR
No. of patents:
4742
Patents:












Patent Number Title Of Patent Date Issued
RE43765 Method for fabricating semiconductor device having trench isolation layer October 23, 2012
A method for fabricating a device isolation structure of a semiconductor device includes the steps of forming a pad oxide layer and a pad nitride layer over a semiconductor substrate including a cell region and a dummy region, etching a portion of the pad nitride layer, the pad oxide lay
RE42409 Method of manufacturing flash memory device May 31, 2011
A method of manufacturing a flash memory device includes the steps of forming trenches by forming a tunnel oxide layer and a conductive layer for a floating gate over a semiconductor substrate, and then etching a portion of the conductive layer, the tunnel oxide layer and the semicon
RE42202 Circuit for controlling an enabling time of an internal control signal according to an operating March 8, 2011
Provided is a circuit for controlling a data bus connecting a bitline sense amplifier to a data sense amplifier in accordance with a variation of an operating frequency of a memory device, being comprised of a pulse width adjusting circuit for varying a pulse width of an input signal in
RE41205 Method of fabricating a semiconductor device April 6, 2010
.[.The present invention relates to a method of fabricating a semiconductor device which reduces.]. .Iadd.The .Iaddend.leakage current .[.by controlling an etch of a field oxide layer when a contact hole is formed. The present invention includes the steps of forming a.]. .Iadd.in a s
RE40172 Multi-bank testing apparatus for a synchronous dram March 25, 2008
A multi-bank testing apparatus for a synchronous DRAM, which allows all banks of the synchronous DRAM to simultaneously carry out their write and read operations in a test mode, thereby being capable of testing the entire bank in order to reduce the test time being likely to increase in
RE40076 Program circuit February 19, 2008
The program circuit according to the present invention can apply a program voltage to the only memory cells which are not programmed during a re-programming operation, thus, the present invention can be prevent a lowering of reliability of the memory cell due to a continued supply of a
8588016 Semiconductor memory device and method for fabricating the same November 19, 2013
A semiconductor memory device includes: a plurality of mats; a plurality of sense amplifier regions disposed on a side of the plurality of mats; and a plurality of main bit lines overlapping with a plurality of secondary bit lines, respectively, in regions for the plurality of mats,
8587366 Semiconductor device November 19, 2013
A semiconductor device includes: a unit configured to, in a period before power up, compare a voltage obtained by dividing a voltage of a first voltage node at a first division ratio with a voltage obtained by dividing a voltage of a second voltage node at a second division ratio and
8582386 Internal voltage generator and semiconductor memory device including the same November 12, 2013
A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed
8582371 Semiconductor memory device and method of operating the same November 12, 2013
A semiconductor memory device according to an aspect of the present disclosure includes a first page buffer coupled to a first even bit line and a first odd bit line, a second page buffer coupled to a second even bit line and a second odd bit line, and a controller configured to cont
8582368 Non-volatile memory device and operating method of the same November 12, 2013
A method for operating a non-volatile memory device includes counting the number of consecutive verify operations performed without a precharge, sensing a temperature, and when the number of verify operations exceeds a set value of verify operations, controlling a level of a sensing bias
8582362 Circuit for precharging bit line and nonvolatile memory device including the same November 12, 2013
A nonvolatile memory device includes a memory cell array configured to comprise a number of cell strings, a number of page buffers each coupled to the cell strings of the memory cell array through bit lines, and a bit line precharge circuit configured to precharge a selected bit line up
8582353 Nonvolatile memory device November 12, 2013
A nonvolatile memory device comprises a memory cell configured to store or output data in a magneto-resistance device in response to a write current applied to a bit line and a source line. A voltage detector is configured to sense potentials loaded in the bit line and the source lin
8581620 Semiconductor device including data output circuit supporting pre-emphasis operation November 12, 2013
A semiconductor device includes a code generator configured to generate a supplementary code with a value changing in response to a variation of an impedance code, a main driver configured to receive an output data and drive the received output data to a data output pad, wherein a drivin
8581397 Substrate for semiconductor package with improved bumping of chip bumps and contact pads and sem November 12, 2013
The present invention relates to a substrate for a semiconductor package and a semiconductor package having the same. A substrate for a semiconductor package includes a substrate body; a contact pad group including a plurality of contact pads parallely arranged at a determined interv
8581369 Semiconductor chip and semiconductor wafer November 12, 2013
A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the
8581337 Semiconductor device for increasing bit line contact area, and module and system including the s November 12, 2013
A semiconductor device including a buried gate is disclosed. In the semiconductor device, a bit line contact contacts a top surface and lateral surfaces of an active region, such that a contact area between a bit line contact and the active region is increased and a high-resistivity
8580678 Method for fabricating semiconductor device with buried gates November 12, 2013
A method for fabricating a semiconductor device includes forming first plugs over a substrate, forming contact holes that expose the first plugs, ion-implanting an anti-diffusion material into the first plugs, and forming second plugs filling the contact holes.
8580669 Method for fabricating semiconductor device November 12, 2013
A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first bit line contact over a semiconductor substrate, forming a second bit line contact that is coupled to the first bit line contact and has a larger width than the
8580636 Highly integrated phase change memory device having micro-sized diodes and method for manufactur November 12, 2013
A highly integrated phase change memory device and a method for manufacturing the same is disclosed. The highly integrated phase change memory device includes a semiconductor substrate having a cell area and a peripheral area with impurity regions formed in the cell area and extendin
8580633 Method for manufacturing a semiconductor device with gate spacer November 12, 2013
A semiconductor device capable of ensuring a sufficient area of a peripheral region by forming a gate spacer to have a uniform thickness in the peripheral region and reducing a fabrication cost by simplifying a mask process and a method of manufacturing the semiconductor device are p
8580582 Semiconductor fabricating device and method for driving the same, and method for fabricating mag November 12, 2013
In a method for fabricating a magnetic tunnel junction, a first magnetic layer is formed on a substrate, and a tunnel insulating layer is formed on the first magnetic layer. Subsequently, a second magnetic layer is formed on the tunnel insulating layer. In the method, the first magnetic
8576645 Semiconductor memory device capable of minimizing current consumption during high speed operatio November 5, 2013
A semiconductor memory device includes a signal processing unit configured to generate a control signal corresponding to burst length information and an output controlling unit configured to control an output of a data strobe signal in response to the control signal.
8576621 Nonvolatile memory device and method of operating the same November 5, 2013
A nonvolatile memory device includes a control unit configured to measure a threshold voltage distribution of each of selected pages between a start voltage and an end voltage by performing a read operation on each page in response to a command set for analyzing the threshold voltage
8575956 Semiconductor device November 5, 2013
A semiconductor device includes an impedance control signal generation unit configured to generate an impedance control signal for controlling an impedance value, a first processing unit configured to process the impedance control signal in response to a first setup value and generate
8575675 Nonvolatile memory device November 5, 2013
A nonvolatile memory device includes a first channel comprising a pair of first pillars vertically extending from a substrate and a first coupling portion positioned under the pair of first pillars and coupling the pair of first pillars, a second channel adjacent to the first channel
8575669 Fabricating technique of a highly integrated semiconductor device in which a capacitor is formed November 5, 2013
The present invention relates to a highly integrated semiconductor device in which a capacitor is formed between adjacent gate patterns by using a nanotube process. A semiconductor memory device according to an example embodiment of the present invention includes a capacitor formed on a
8575586 Resistive memory device and method for manufacturing the same November 5, 2013
A resistive memory device and a method for manufacturing the same are disclosed. The resistive memory device includes a lower electrode formed over a substrate, a resistive layer disposed over the lower electrode, an upper electrode formed over the resistive layer, and an oxygen-diffusio
8574988 Method for forming semiconductor device November 5, 2013
A method for forming a highly integrated semiconductor device having multiplayer conductive lines is presented. The method includes the operations of forming, etching, burying and forming. The first forming operation includes forming a line-type conductive layer on a semiconductor su
8574986 Method for fabricating nonvolatile memory device November 5, 2013
A method for fabricating a nonvolatile memory device includes forming a substrate structure having a tunnel dielectric layer and a floating-gate conductive layer formed over an active region defined by a first isolation layer forming a first inter-gate dielectric layer and a first co
8574820 Method for fabricating semiconductor device November 5, 2013
A method for fabricating a semiconductor device includes: forming a first photoresist pattern with a first opening over an etch target layer; forming a second photoresist pattern with a plurality of second openings over the first photoresist pattern; and forming a plurality of patterns
8574819 Method for forming fine pattern November 5, 2013
A method includes forming a hard mask layer over an etch target layer that extends across first and second regions, forming a sacrificial layer pattern over the hard mask layer of the first region, removing the sacrificial layer pattern after forming a spacer pattern on side walls th
8570801 Method of programming a semiconductor memory device October 29, 2013
A method of programming a semiconductor memory device includes the steps of grouping memory cells in accordance with levels of threshold voltages to be programmed, programming the memory cell groups by sequentially applying program voltages to the memory cell groups, and program-veri
8570796 Nonvolatile memory cell, nonvolatile memory device and method for driving the same October 29, 2013
A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the
8570109 Ring oscillator for generating oscillating clock signal October 29, 2013
A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.
8570097 Semiconductor integrated circuit October 29, 2013
A semiconductor integrated circuit includes a first pad configured to receive a first voltage, a second pad configured to receive a second voltage, an internal voltage generation circuit configured to generate a third voltage having the same voltage level as the first voltage in resp
8570094 Semiconductor integrated circuit and method for driving the same October 29, 2013
A semiconductor integrated circuit includes a command generating unit configured to generate a plurality of second commands in response to a first command, each second command for indicating an operation sections of a corresponding anti-fuse circuit, and a plurality of anti-fuse circ
8569832 Vertical transistor having first and second tensile layers October 29, 2013
A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and around the lower end portion of the pillar type active pattern, and a second tensile layer is
8569817 Semiconductor device and method for fabricating the same October 29, 2013
A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive
8566685 Command control circuit, integrated circuit having the same, and command control method October 22, 2013
A command control circuit includes a command decoder configured to decode a command and generate an internal command, an error check unit configured to detect an error in the command and an address by using check data and generate an error check signal in response to the detection, a
8565027 Multi-chip package and operating method thereof October 22, 2013
A multi-chip package includes a voltage generating circuit configured to generate a power source voltage and a plurality of memory chips coupled to the voltage generating circuit to each receive the power source voltage, wherein the memory chips are each configured to postpone an ope
8565022 Memory system and method of operating the same October 22, 2013
A memory system includes a flash memory device including a first memory block group on which a least significant bit (LSB) program operation has been performed and a program operation on another bit has not been performed and a second memory block group on which both the LSB program
8564341 DLL circuit and method of controlling the same October 22, 2013
A delayed lock loop (DLL) circuit includes: a phase conversion control unit configured to latch and drive a phase comparison signal in response to the input of a delay enable signal, and output the driven signal as a phase conversion control signal. A phase converting unit configured to
8564138 Semiconductor integrated circuit having a three-dimensional (3D) stack package structure October 22, 2013
A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semicond
8563960 Phase change random access memory and method for manufacturing the same October 22, 2013
A phase change random access memory includes a semiconductor substrate having a bottom electrode formed over the semiconductor substrate; and a phase change layer formed over the bottom electrode. The phase change layer a first phase change layer formed over the bottom electrode and
8563413 Semiconductor device with buried gate and method for fabricating the same October 22, 2013
A Semiconductor device includes a substrate having an active region defined by a device isolation layer, a trench formed by etching the active region and the device isolation layer, a buried gate filling a portion of the trench, an interlayer insulation layer formed over the buried g
8302035 Method for verifying optical proximity correction October 30, 2012
A method for verifying an optical proximity correction includes: performing an optical proximity correction on a target pattern layout; performing a primary verification on the target pattern layout which has undergone the optical proximity correction; performing a secondary verifica
8300486 Temperature detection circuit of semiconductor memory apparatus October 30, 2012
A temperature detection circuit of a semiconductor memory apparatus includes a fixed period oscillator, a temperature variable signal generating unit and a counting unit. The oscillator is configured to generate a fixed period oscillator signal when an enable signal is enabled. The t
8300482 Data transfer circuit and semiconductor memory device including the same October 30, 2012
A data transfer circuit has a reduced number of lines for transferring a training pattern used in a read training for high speed operation, by removing a register for temporarily storing the training pattern, and a semiconductor memory device including the data transfer circuit. The data
8300481 Apparatus and method for transmitting/receiving signals at high speed October 30, 2012
A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage

 
 
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