| Patent Number |
Title Of Patent |
Date Issued |
| RE40172 |
Multi-bank testing apparatus for a synchronous dram |
March 25, 2008 |
| A multi-bank testing apparatus for a synchronous DRAM, which allows all banks of the synchronous DRAM to simultaneously carry out their write and read operations in a test mode, thereby being capable of testing the entire bank in order to reduce the test time being likely to increase in |
| RE40076 |
Program circuit |
February 19, 2008 |
| The program circuit according to the present invention can apply a program voltage to the only memory cells which are not programmed during a re-programming operation, thus, the present invention can be prevent a lowering of reliability of the memory cell due to a continued supply of a |
| 7403431 |
Method of reading a flash memory device |
July 22, 2008 |
| A method of reading a flash memory device wherein the status of a predetermined cell is read in such a way that a plurality of page buffers connected to a memory cell array through a plurality of bit lines are divided into at least two group, and the page buffers are sequentially dri |
| 7402864 |
Method for forming a DRAM semiconductor device with a sense amplifier |
July 22, 2008 |
| A method for forming a sense amplifier of a semiconductor device prevents bit lines from being bridged to each other by a stepped portion created on an insulation interlayer due to irregular density of a P-type impurity, which is ion-implanted into an insulation interlayer in a P+ pi |
| 7400165 |
Method for calibrating a driver and on-die termination of a synchronous memory device |
July 15, 2008 |
| An improved driver and ODT impedance calibration techniques of a synchronous memory device are provided. The impedance calibration is performed by generating a calibration enable signal showing a calibration operation mode entry. The code signals for an ODT calibration are generated |
| 7399570 |
Water-soluble negative photoresist polymer and composition containing the same |
July 15, 2008 |
| Photoresist patterns are formed using a photoresist composition, which includes water, a negative photoresist polymer having a salt-type repeating unit, and a photoacid generator, so that a developing process can be performed not by using conventional TMAH solution but by using water |
| 7397115 |
Folding chip planar stack package |
July 8, 2008 |
| A folding chip planar stack package is realized by employing folding chips. The folding chip planar stack package includes a substrate, first and second semiconductor chips attached to an upper surface of the substrate while being folded and spaced in parallel to each other, a bondin |
| 7396772 |
Method for fabricating semiconductor device having capacitor |
July 8, 2008 |
| A method for fabricating a semiconductor device includes: providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level; forming first, second, and third insulation layers over the bit line, the second insulation layer being a |
| 7396751 |
Method for manufacturing semiconductor device |
July 8, 2008 |
| A method for manufacturing a semiconductor device includes forming a second storage node contact hole with a mask for storage node and securing an overlay margin between a storage node contact hole and a storage node with a hard mask layer that serves as a hard mask as well as an ant |
| 7396738 |
Method of forming isolation structure of flash memory device |
July 8, 2008 |
| A method of forming a semiconductor memory device includes providing a semiconductor substrate having a cell region and a peripheral region. A gate dielectric layer is formed over the semiconductor substrate in the peripheral region. An insulating layer is formed over the gate dielectric |
| 7396725 |
Method of manufacturing semiconductor device |
July 8, 2008 |
| A method of manufacturing a semiconductor device includes forming an insulating layer, a first conductive layer, a dielectric layer and a capping conductive layer over a semiconductor substrate in which a cell region is defined. The capping conductive layer and the dielectric layer i |
| 7395475 |
Circuit and method for fuse disposing in a semiconductor memory device |
July 1, 2008 |
| A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test mode enable confirmation section for informing whether a test mode is enabled; and a f |
| 7394722 |
Method for controlling data output timing of memory device and device therefor |
July 1, 2008 |
| Disclosed is a device for controlling data output of a memory device using a DLL clock signal, the device comprising: an output driver for outputting data; and a CAS latency control unit for generating a signal adjusting an operation timing of the output driver depending on CAS laten |
| 7394718 |
Semiconductor memory device having a global data bus |
July 1, 2008 |
| There is provided a semiconductor design technology, particularly, a bus line arrangement method of global data bus in the semiconductor memory device. According to the invention, skew by lines can be not occurred, or can be minimized upon an issuance thereof. Further, upon its issuance, |
| 7394712 |
Semiconductor memory device performing self refresh operation |
July 1, 2008 |
| The present invention relates to a semiconductor memory device to execute a refresh operation in such a manner that an entry and an exit of a self refresh mode is carried out. The present invention uses only external clock signals without a clock enable signal or an auto refresh command |
| 7394705 |
Internal voltage supplier for memory device |
July 1, 2008 |
| Disclosed is an internal voltage supplier for the memory device, the internal voltage supplier comprising: a first switching means for selecting one of a first voltage generated from an interior of the memory device and a second voltage applied from an exterior of the memory device; |
| 7394494 |
Sub-sampling apparatus and method and image sensor employing the same |
July 1, 2008 |
| The present disclosure relates to an address sub-sampling apparatus and method, and an image sensor employing the same. An address sub-sampling apparatus includes a counting unit that generates a binary address of N bits, N being a natural number larger than 2. The address sub-sampling |
| 7394285 |
Circuit for driving bus |
July 1, 2008 |
| A bus driving circuit includes a majority voter unit for comparing the number of logic high level bits with the number of logic low level bits among a predetermined number of bits of data; a latch unit for latching a first output signal in response to the compared result; and a flip-flop |
| 7393767 |
Method for implanting a cell channel ion of semiconductor device |
July 1, 2008 |
| A method for implanting a cell channel ion of semiconductor device is disclosed. In accordance with the method, the bit line contact region and the edge portion of the channel region adjacent to the bit line contact region in the cell region are subjected to a selective cell channel |
| 7393744 |
Method of manufacturing dielectric film of flash memory device |
July 1, 2008 |
| A method of manufacturing a dielectric film of a flash memory device, including the steps of providing a semiconductor substrate having floating gates formed therein, performing an oxidization process in a decompression state to form a first oxide film of a thin film on the semicondu |
| 7391671 |
Data input device for use in semiconductor memory device |
June 24, 2008 |
| A data input device for use in a semiconductor memory device includes a synchronization control unit for receiving a data strobe signal with which a data is synchronized in order to generate a synchronization signal in response to a driving signal; and a synchronization unit for stor |
| 7391670 |
Semiconductor memory device |
June 24, 2008 |
| A semiconductor memory device is provided. The semiconductor memory device includes an active commander for generating an active command upon receiving a plurality of control signals, a first signal generator configured to receive the active command, and generate a first latch signal |
| 7391663 |
Structure and method for measuring the channel boosting voltage of NAND flash memory at a node b |
June 24, 2008 |
| Provided is a structure for testing a NAND flash memory including a string select transistor, a source select transistor, flash memory cells connected in series between the string select transistor and a source select transistor and a measurement pad coupled to a node between a flash |
| 7391660 |
Address path circuit with row redundant scheme |
June 24, 2008 |
| An address path circuit with a row redundant scheme may include an address buffer for buffering an external address to output an internal address, a command buffer for buffering a plurality of external commands, a pre-latch unit for pre-latching the internal address from the address |
| 7391658 |
Internal voltage generator capable of regulating an internal voltage of a semiconductor memory d |
June 24, 2008 |
| An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage and a level of a |
| 7391248 |
Duty cycle corrector of delay locked loop |
June 24, 2008 |
| Provided is a digital duty cycle corrector capable of generating a clock signal with the rate of duty 50:50, by means of three or more duty cycle correction circuits assigning different weight values to first and second clock signals that are different in duty cycle each other in order t |
| 7391106 |
Stack type package |
June 24, 2008 |
| A stack type semiconductor package uses rigid, C-shaped guide substrates that hold semiconductor packages stacked in place and which also provide signal pathways between the stacked semiconductors and contact surfaces of the package. The C-shaped guide eliminate short circuits caused by |
| 7390716 |
Method of manufacturing flash memory device |
June 24, 2008 |
| A method of manufacturing a flash memory device. An etch process for controlling the effective field height of isolation layers is performed using a dry etch process on condition that an excessive amount of polymer is generated, thus forming first spacers on sidewalls of a floating gate |
| 7390714 |
Method of manufacturing semiconductor device having tungsten gates electrode |
June 24, 2008 |
| Disclosed herein is a method of manufacturing semiconductor devices. The method includes the steps of forming a gate oxide film, a polysilicon film and a nitride film on a semiconductor substrate, and patterning the gate oxide film, the polysilicon film and the nitride film to form poly |
| 7390611 |
Photoresist coating composition and method for forming fine pattern using the same |
June 24, 2008 |
| A photoresist coating composition that includes a compound represented by Formula 1 and an aqueous solvent, and a method for forming a fine pattern by coating the composition on a photoresist pattern to effectively reduce a size of a photoresist contact hole and a space, which can be app |
| 7388804 |
Semiconductor memory device for driving a word line |
June 17, 2008 |
| A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlli |
| 7388799 |
Semiconductor memory device |
June 17, 2008 |
| A semiconductor memory device for consuming a uniform amount of current includes a memory cell block including a N normal wordline and a M preliminary wordline; a refresh address counting block for outputting a refresh address, having a plurality of bits, corresponding to the N norma |
| 7388797 |
Semiconductor memory device |
June 17, 2008 |
| An apparatus for detecting a defect of a data transfer line in a semiconductor memory device, including a data transfer unit for transferring data between a local I/O line and a global I/O line; a data transfer controller for controlling the data transfer unit by generating a read si |
| 7388415 |
Delay locked loop with a function for implementing locking operation periodically during power d |
June 17, 2008 |
| A Delay Locked Loop (DLL) having a function of periodically executing a locking operation during a power down mode and a locking operation method of the same, which includes a global clock generator, a clock delay unit, and a power down control unit. The power down control unit, in respo |
| 7388240 |
Non-volatile memory device capable of preventing damage by plasma charge |
June 17, 2008 |
| A non-volatile memory device for preventing damage by plasma charges includes a gate electrode formed on a predetermined region of a semiconductor substrate, a source/drain region which is overlapped with the gate electrode and formed in a first well region of the semiconductor subst |
| 7387941 |
Method for fabricating semiconductor device |
June 17, 2008 |
| A method for manufacturing a semiconductor device in accordance with an embodiment of the present invention provides a channel region formed over a device isolation structure to form a semiconductor device including a SOI (Silicon-on-Insulator) channel structure, thereby decreasing ion |
| 7387929 |
Capacitor in semiconductor device and method of manufacturing the same |
June 17, 2008 |
| The present invention relates to a capacitor in semiconductor device and a method of manufacturing the same, wherein, owing to formation of a lower electrode and an upper electrode into a stack structure of a poly-silicon layer and an aluminum (Al) layer and formation of an alumina ( |
| 7385860 |
Data output circuit of synchronous memory device |
June 10, 2008 |
| A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits |
| 7385852 |
Circuit for generating step-up voltage in non-volatile memory device |
June 10, 2008 |
| A circuit for generating a step-up voltage, in which it can reduce ripples. The circuit includes a high voltage transfer switch, a high voltage switching unit that pumps a high voltage in response to a clock signal and switches the high voltage transfer switch, a high voltage switchi |
| 7385850 |
Method of programming and verifying cells of a nonvolatile memory and relative NAND FLASH memory |
June 10, 2008 |
| A method of programming cells in a nonvolatile memory is based upon a Global Verify operation and a Byte-by-byte Verify operation. The cells of a destination page of the nonvolatile memory are programmed, and logic values stored in the programmed cells of a source page of the same memory |
| 7385428 |
Digital delay locked loop capable of correcting duty cycle and its method |
June 10, 2008 |
| An apparatus for adjusting a clock signal, including: a clock multiplexing unit for receiving an external clock signal, an external clock bar signal and a feed-backed clock signal in order to select one of the external clock signal and the external clock bar signal as an output signal of |
| 7384846 |
Method of fabricating semiconductor device |
June 10, 2008 |
| A method of fabricating semiconductor devices. Upon formation of a trench for isolation in a cell region, a hard mask film is used as an etch mask. It is thus possible to prevent attacks of a lower layer due to deformation or loss of the etch mask. |
| 7384844 |
Method of fabricating flash memory device |
June 10, 2008 |
| A method of fabricating a flash memory device includes defining a high voltage region and a low voltage region on a substrate. The high voltage region provides an area for one or more first transistors configured to operation at a first voltage, the low voltage region providing an area |
| 7384823 |
Method for manufacturing a semiconductor device having a stabilized contact resistance |
June 10, 2008 |
| Disclosed is a method for forming a storage node contact of a semiconductor device. In such a method, there is provided a substrate formed with gates and source/drain regions. A landing plug poly is formed between the gates, and an insulating interlayer is formed over the entire surf |
| 7382677 |
Memory device having internal voltage supply providing improved power efficiency during active m |
June 3, 2008 |
| A internal voltage generator in a semiconductor memory device has a first and second internal voltage generators. The first internal voltage generator outputs a first signal having a first voltage level to internal circuits of the memory device during an active mode of the memory device |
| 7382671 |
Method for detecting column fail by controlling sense amplifier of memory device |
June 3, 2008 |
| Disclosed is a method for detecting a column fail by controlling a sense amplifier of a memory device. The method includes the steps of enabling a word line of a memory cell of the memory device, adjusting a timing of a high-level driving voltage and a low-level driving voltage applied t |
| 7382660 |
Method for accessing a multilevel nonvolatile memory device of the flash NAND type |
June 3, 2008 |
| Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bi |
| 7382641 |
FeRAM for high speed sensing |
June 3, 2008 |
| A non-volatile ferroelectric memory device senses a cell data at high speed. Preferably, the non-volatile ferroelectric memory device includes a plurality of cell array blocks, a plurality of sense amplifier units, a plurality of sense amplifier units, a plurality of local data buses, a |
| 7381652 |
Method of manufacturing flash memory device |
June 3, 2008 |
| A method of manufacturing a flash memory device which an etch-prevention layer, first and second interlayer insulating layers, and first, second and third hard mask layers are sequentially formed on a semiconductor substrate. The third hard mask layer is etched to expose a portion of a |
| 7381640 |
Method of forming metal line and contact plug of flash memory device |
June 3, 2008 |
| A method of forming a metal line and a contact plug of a flash memory device, wherein if first, second, and third etch processes are performed on an anti-reflection film and regions (a region in which a contact plug through which a gate is exposed is formed/a region in which a contact |
