| Patent Number |
Title Of Patent |
Date Issued |
| RE30604 |
Reusable fixture for an integrated circuit chip |
May 5, 1981 |
| A reusable fixture for a segment of a film strip having a flexible beam lead frame mounted on the segment and an integrated circuit chip bonded to the inner portions of the leads of the lead frame. The fixture is made from an integral laminar layer of a suitable material. The improvement |
| D287591 |
Wall mounted factory data collection terminal or similar article |
January 6, 1987 |
|
| D287590 |
Desk mounted factory data collection terminal or similar article |
January 6, 1987 |
|
| D280198 |
Desktop computer system |
August 20, 1985 |
|
| D279901 |
Low profile keyboard or similar article |
July 30, 1985 |
|
| D272353 |
Video terminal or similar article |
January 24, 1984 |
|
| D272247 |
Desktop computer system |
January 17, 1984 |
|
| D271356 |
Magnetic tape reel storage rack |
November 15, 1983 |
|
| D270357 |
Document holder for a display terminal |
August 30, 1983 |
|
| D270026 |
Tilt base support for CRT terminal or the like |
August 9, 1983 |
|
| D263222 |
Disk cartridge |
March 2, 1982 |
|
| D262800 |
Magazine for holding slide mounts for film segments or the like |
January 26, 1982 |
|
| D253445 |
Data processing work station or the like |
November 20, 1979 |
|
| D252875 |
Facade for enclosing data processing apparatus or the like |
September 11, 1979 |
|
| D245594 |
Document handling cart or similar article |
August 30, 1977 |
|
| D243771 |
Computer or similar article |
March 22, 1977 |
|
| D243518 |
Multiple use service cart |
March 1, 1977 |
|
| D243254 |
Computer or similar article |
February 1, 1977 |
|
| 5136500 |
Multiple shared memory arrangement wherein multiple processors individually and concurrently acc |
August 4, 1992 |
| A memory controller in which a number of local memories are primarily dedicated to the shared use of a number of local processors of a data processing system to increase the efficiency of use of both the processors and memories. A controller is associated with each local memory to contro |
| 5036456 |
Apparatus for controlling concurrent operations of a system control unit including activity regi |
July 30, 1991 |
| In a data processing system having a system controller unit (SCU) which interfaces a plurality of equipments with a memory unit, the SCU determines which of the equipments will be permitted to communicate with the SCU or memory unit in response to a request from the equipments. The S |
| 4837738 |
Address boundary detector |
June 6, 1989 |
| An address boundary detector is disclosed that functions with an arithmetic logic unit (ALU) in a computer processor while the ALU generates addresses by adding an offset or displacement to a base address. The detector monitors bits of addresses to determine whether a data item can be |
| 4751630 |
Interactive terminal system using a prepoll prior to transferring information from the controlle |
June 14, 1988 |
| An interactive terminal system transfers information at 750,000 bits per second between a central system and a number of work stations, all coupled in common to a single conductor coaxial bus. The central system prepolls an addressed work station before sending a block of information. Th |
| 4739473 |
Computer memory apparatus |
April 19, 1988 |
| A memory subsystem couples to a bus in common with a central processing unit and processes memory requests received therefrom. The subsystem includes a number of addressable memory module units or stacks each having a number of word blocks of dynamic random access memory (DRAM) chips |
| 4731738 |
Memory timing and control apparatus |
March 15, 1988 |
| A memory board can be assembled with one, two or more rows of memory chips to provide a corresponding number of different memory capacities for expanding the capacity of main memory which resides on a basic logic board containing the processing units and other units of a system. The memo |
| 4727934 |
Data collection terminal designed for a hostile environment |
March 1, 1988 |
| A data entry terminal for use in a hostile environment is sealed from the outside environment. The terminal has a housing made up of a front panel, shroud and base plate that are fastened together in two different orientations to facilitate desk top and wall mounting, and electronic |
| 4727486 |
Hardware demand fetch cycle system interface |
February 23, 1988 |
| A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the |
| 4725946 |
P and V instructions for semaphore architecture in a multiprogramming/multiprocessing environmen |
February 16, 1988 |
| In a computer system having a plurality of processors and processes, a semaphore architecture for communication with and between the processes in order to effects coordination and cooperation between processes. The invention is implemented in firmware and software, and divides the work o |
| 4724519 |
Channel number priority assignment apparatus |
February 9, 1988 |
| A data processing system has a system bus network which includes a distributed priority network for transferring data asynchronously between a number of subsystems which couple to the bus. Each subsystem includes priority logic circuits coupled to receive a group of priority signals |
| 4724431 |
Computer display system for producing color text and graphics |
February 9, 1988 |
| The invention pertains to a method and apparatus to provide for the display of characters and graphics in color. The invention includes three bit map memories which store graphics information for different colors, one character generator driven from a text memory for display of text, and |
| 4711024 |
Method for making testable electronic assemblies |
December 8, 1987 |
| A method for achieving printed circuit (PC) board-level testability through electronic component-level design using available technological methods to effect a state of transparency during test, allowing precise verification and diagnosis on a component-by-component basis. Applicable to |
| 4703417 |
Call instruction for ring crossing architecture |
October 27, 1987 |
| In combination with a multiprocessing/multiprogramming computer system having a ring protection mechanism for protecting computer programs from unauthorized access, a new call instruction architecture is implemented partly in firmware and partly in hardware. Also, a new stack mechanism |
| 4703322 |
Variable loadable character generator |
October 27, 1987 |
| A Loadable Character Generator whose operation can be changed to suit various needs, such as foreign language requirements, without hardware change and with minimum hardware. The character generator translates the character code of a character to be displayed to the dot pattern for that |
| 4702542 |
Latch and lock electrical connector housing |
October 27, 1987 |
| What is disclosed is a housing for a D-shell connector that comprises two housing parts that snap and lock securely together and can later be separated without the use of tools. In addition, the housing has an integral strain relief cable clamp. Internal or external latching arms cap |
| 4701863 |
Apparatus for distortion free clearing of a display during a single frame time |
October 20, 1987 |
| A graphics display is cleared by apparatus forcing binary ZERO's into all locations of the bit map memories between successive vertical synchronization operations during a write refresh operation. |
| 4695943 |
Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization |
September 22, 1987 |
| A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which of |
| 4695923 |
Printed circuit board bolt-on power distribution system |
September 22, 1987 |
| A bolt-on configuration of a power distribution system utilizes an apparatus which connects a first element to a second element, the second element having a hole, such that a minimum predetermined force exists at the connection between the first element and the second element. The ap |
| 4688868 |
Grounding gasket for D-shell connector |
August 25, 1987 |
| A pair of conductive ground clips each having a plurality of flexible fingers, are slid into an interference engagement with the ends of a flange of a D-shell connector. The ground clip equipped connector is held in a plastic connector housing which is latched to a conductive plate by |
| 4686621 |
Test apparatus for testing a multilevel cache system with graceful degradation capability |
August 11, 1987 |
| A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be |
| 4685032 |
Integrated backplane |
August 4, 1987 |
| An electronic system is packaged to provide a single etched backplane. Bus bars are physically fastened to bushings which are soldered to the backplane power etch lines to provide power to the system.Printed circuit boards are plugged into connectors mounted on the backplane for receivin |
| 4683466 |
Multiple color generation on a display |
July 28, 1987 |
| A color display graphics system includes three bit map memories for storing bits representing red, green and blue colors respectively. Combinations of bits from the same address locations of each bit map memory display a pixel which could be any one of eight colors: black, blue, green, c |
| 4680702 |
Merge control apparatus for a store into cache of a data processing system |
July 14, 1987 |
| A register unit includes means for storing pertinent data relative to a plurality of cache transactions, identifying the zones of an addressed word block which is the subject of the individual transactions. These data are selectively extracted from the register to control the merging of |
| 4677548 |
LSI microprocessor chip with backward pin compatibility and forward expandable functionality |
June 30, 1987 |
| A chip implemented in new technology is designed to include expandable levels of new functionality. The chip includes compatibility circuits which connect to a number of pins which are unused in the chip it replaces in an existing computer system. The compatibility circuits connect to |
| 4672360 |
Apparatus and method for converting a number in binary format to a decimal format |
June 9, 1987 |
| A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is disclosed. Also disclosed is a method and apparatus for speeding conversion of a number in binary format to decimal format by first stripping l |
| 4670835 |
Distributed control store word architecture |
June 2, 1987 |
| Apparatus that provides interrupt operation in a central processor based system wherein internal subsystems are operated via addresses generated by a next address generator in the processor and sent to control stores associated with each subsystem to thereby read out firmware instruction |
| 4669057 |
Data collection terminal interrupt structure |
May 26, 1987 |
| A data collection terminal includes a microprocessor, a memory and a number of devices coupled to a system bus. An interrupt controller processes the device interrupt requests by sending a vector address out on the system bus to enable the microprocessor to branch to a microprogram to pr |
| 4667329 |
Diskette subsystem fault isolation via video subsystem loopback |
May 19, 1987 |
| A data processing system includes a cathode ray tube (CRT) display subsystem and a floppy disk subsystem. The logic of both systems are verified by generating and transferring a fixed format stream of data bits from the CRT display subsystem to the floppy disk subsystem in modified f |
| 4667288 |
Enable/disable control checking apparatus |
May 19, 1987 |
| A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be |
| 4665822 |
Squeegee for screen process printers for printing of dielectric and metallic pastes for single a |
May 19, 1987 |
| A squeegee is utilized in a screen process printer for microcircuits and components thereof. The type is one in which the squeegee and a flat stationary screen are mounted with the squeegee movable and in a wiping action makes contact with the screen so as to press a paste through op |
| 4665482 |
Data multiplex control facility |
May 12, 1987 |
| A data processing system includes a central processing unit (CPU), an input/output microprocessor, a main memory and a number of mass storage controllers. A block of information is transferred between one of the mass storage controllers and main memory during data multiplex control (DMC) |
| 4665481 |
Speeding up the response time of the direct multiplex control transfer facility |
May 12, 1987 |
| A microprogrammed data processing system includes a central processing unit (CPU), a main memory and a number of mass storage controllers. A block of information is transferred between main memory and one of the mass storage controllers during data multiplex control (DMC) cycles. The mai |
