| Patent Number |
Title Of Patent |
Date Issued |
| RE35313 |
Semiconductor integrated circuit with voltage limiter having different output ranges from normal |
August 13, 1996 |
| In a voltage converter which is disposed in a semiconductor integrated circuit so as to lower an external supply voltage and to feed the lowered voltage to a partial circuit of the integrated circuit, the voltage converter is constructed so as to produce an output voltage suited to an |
| RE34060 |
High speed semiconductor memory device having a high gain sense amplifier |
September 8, 1992 |
| In a static type RAM, a sense amplifier includes first and second dissymmetric type differential amplifier circuits each of which has a pair of differential transistors and an active load circuit such as a current mirror circuit connected to the drains of the differential transistors. |
| 6381680 |
Data processing system with an enhanced cache memory control |
April 30, 2002 |
| A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer |
| 6272596 |
Data processor |
August 7, 2001 |
| A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main. The data processor also includes an instruction controller reading out an instruc |
| 5974533 |
Data processor |
October 26, 1999 |
| A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an |
| 5822761 |
Data processing system which controls operation of cache memory based and the address being acce |
October 13, 1998 |
| A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer |
| 5809274 |
Purge control for ON-chip cache memory |
September 15, 1998 |
| A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an |
| 5712859 |
Semiconductor integrated circuit |
January 27, 1998 |
| In a voltage converter which is disposed in a semiconductor integrated circuit so as to lower an external supply voltage and to feed the lowered voltage to a partial circuit of the integrated circuit; the voltage converter is constructed so as to produce an output voltage suited to an |
| 5680631 |
Data processor with on-chip cache memory and purge controller responsive to external signal for |
October 21, 1997 |
| A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an |
| 5638508 |
Method and a system for processing a log record |
June 10, 1997 |
| A data processing system for processing transactions, wherein a log record to be used for recovery of the system is written into a log file for system recovery in synchronism with the end of a transaction, and log records other than resident information are is written for a plurality of |
| 5619677 |
Data processing system with an enhanced cache memory control |
April 8, 1997 |
| A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer |
| 5581698 |
Semiconductor integrated circuit device with test mode for testing CPU using external Signal |
December 3, 1996 |
| An output gate means is provided which is capable of outputting individual signals selectively to an internal bus; the individual signals are interchanged among a plurality of functional modules connected to the internal bus which is interfaced with an external circuit. An input gate |
| 5566185 |
Semiconductor integrated circuit |
October 15, 1996 |
| In a voltage converter which is disposed in a semiconductor integrated circuit so as to lower an external supply voltage and to feed the lowered voltage to a partial circuit of the integrated circuit; the voltage converter is constructed so as to produce an output voltage suited to an |
| 5509133 |
Data processing system with an enhanced cache memory control |
April 16, 1996 |
| A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer |
| 5502825 |
Data processing system with an enhanced cache memory control |
March 26, 1996 |
| A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer |
| 5497482 |
Data processor in which external sync signal may be selectively inhibited |
March 5, 1996 |
| An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is |
| 5493686 |
Data processor in which external sync signal may be selectively inhibited |
February 20, 1996 |
| An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is |
| 5493656 |
Microcomputer with dynamic bus controls |
February 20, 1996 |
| A microcomputer includes one or more registers therein. These registers are provided for defining a specific address area. When a processor unit in the microcomputer accesses an address in the specific address area, it acknowledges the access to change the bus width and/or bus cycle of t |
| 5493572 |
Semiconductor integrated circuit with voltage limiter having different output ranges for normal |
February 20, 1996 |
| In a voltage converter which is disposed in a semiconductor integrated circuit so as to lower an external supply voltage and to feed the lowered voltage to a partial circuit of the integrated circuit; the voltage converter is constructed so as to produce an output voltage suited to an |
| 5479625 |
Ring systolic array system for synchronously performing matrix/neuron computation using data tra |
December 26, 1995 |
| A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) corresponds to an area (such as a status register in the above-mentioned micr |
| 5468998 |
Resin molded type semiconductor device having a conductor film |
November 21, 1995 |
| A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package c |
| 5414825 |
Method of programming a semiconductor memory device within a microcomputer address space |
May 9, 1995 |
| In a one-chip microcomputer, an electrically programmable read only memory (EPROM) is formed together with a read-only memory (ROM) and random access memory (RAM) on one semiconductor substrate. Data such as fixed data necessary in the microcomputer can be changed by the use of the EPROM |
| 5398319 |
Microprocessor having apparatus for dynamically controlling a kind of operation to be performed |
March 14, 1995 |
| A microprocessor including instruction decoding apparatus, instruction execution apparatus and information holding apparatus. The microprocessor performs a first step of storing information specifying the kind of operation to be performed by the instruction execution apparatus, upon |
| 5398047 |
Semiconductor integrated circuit device including high-speed operating circuit and low-speed ope |
March 14, 1995 |
| The semiconductor integrated circuit device formed on one semiconductor substrate employs a plurality of first and second circuit blocks constituting functions of the same kind. The first and second circuit blocks, however, are implemented with respectively different types of circuit |
| 5379423 |
Information life cycle processor and information organizing method using it |
January 3, 1995 |
| An information life cycle management system and an information organizing method using the computer system stores information objects composed of a database and program, and a data processing device for processing an information object which is a block of the information in the storage |
| 5377136 |
Semiconductor integrated circuit device with built-in memory circuit group |
December 27, 1994 |
| A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by |
| 5367490 |
Semiconductor integrated circuit device with two variable delay lines in writing circuit control |
November 22, 1994 |
| Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided lo |
| 5349672 |
Data processor having logical address memories and purge capabilities |
September 20, 1994 |
| A data processor is used with a main memory that stores operand data and instructions. The data processor itself includes two cache memories, one of which stores logical instruction addresses and corresponding instructions while the other stores logical operand addresses and correspo |
| 5341481 |
Method and apparatus for dynamically changing bus size using address register means and comparat |
August 23, 1994 |
| A microcomputer includes one or more registers therein. These registers are provided for defining a specific address area. When a processor unit in the microcomputer accesses an address in the specific address area, it acknowledges the access to change the bus width and/or bus cycle of t |
| 5323242 |
Carrier signal generating circuit in video signal recording/reproducing apparatus |
June 21, 1994 |
| In a video signal apparatus, a carrier signal generating circuit includes a VCO for generating a signal having a frequency at least twice that of a carrier signal necessary for conversion to a lower band with a sub-carrier in an NTSC system, a one-half divider circuit for dividing the VC |
| 5317704 |
Storage relocating method and hierarchy storage system utilizing a cache memory |
May 31, 1994 |
| A method and apparatus for relocating a storage such that a physical address area of the storage, which is allocated to an absolute address area, is replaced with a new physical address area. This relocation process is performed with a Floating Address Register for translating an abs |
| 5299287 |
Information processing system |
March 29, 1994 |
| A problem solving system including apparatus for representing a relationship between a goal including subgoals and its lower level subgoals and for achieving the goal as a strategy of a first kind. Apparatus is provided for repetitively dividing a goal including subgoals into its low |
| 5293077 |
Power switching circuit |
March 8, 1994 |
| When a current that flows into a power output element is greater than a predetermined value, pulse width-modulated signals are formed which vary in inverse proportion to the current value in order to drive the power output element. When an excess current flows into the power output e |
| 5291419 |
Method for diagnosing the life of a solder connection |
March 1, 1994 |
| A method for evaluating the life of a connection between members including the steps of extracting parameters defining the shearing strain of a predetermined model representing the connection thereby to calculate the values of plural shearing strains of the connection, calculating the |
| 5274809 |
Task execution control method for a multiprocessor system with enhanced post/wait procedure |
December 28, 1993 |
| Task execution control for a multiprocessor wherein at a time point when a post issue task ends the use of a shared resource, the shared resource is released, another task which is running on another processor is allowed to lock the shared resource, and thereafter the task is made ready. |
| 5265045 |
Semiconductor integrated circuit device with built-in memory circuit group |
November 23, 1993 |
| A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by |
| 5261065 |
Input/output processing method in a database management system |
November 9, 1993 |
| With respect to input/output requests; a microprogram controls collection of data according to the data format; data accessing divides the requests for every recording medium and performs asynchronous processing; an on-line process is carried out in view of the processing priority order |
| 5257352 |
Input/output control method and system |
October 26, 1993 |
| An input/output control apparatus connected to a plurality of input/output units such as disc systems and an input/output control method. A cache memory is divided into a plurality of storage areas for data management. Data stored in the disc systems are stored in the storage areas. In |
| 5249276 |
Address translation apparatus having a memory access privilege check capability data which uses |
September 28, 1993 |
| An address translation apparatus which includes a memory for storing a plurality of physical addresses, and a content addressable memory unit which stores a plurality of signal pairs that correspond to the plurality of physical addresses, each of the signal paris includes a logical addre |
| 5229642 |
Resin molded type semiconductor device having a conductor film |
July 20, 1993 |
| A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package c |
| 5228139 |
Semiconductor integrated circuit device with test mode for testing CPU using external signal |
July 13, 1993 |
| An output gate means is provided which is capable of outputting individual signals selectively to an internal bus; the individual signals are interchanged among a plurality of functional modules connected to the internal bus which is interfaced with an external circuit. An input gate |
| 5218693 |
Timer unit and data processing apparatus including the same |
June 8, 1993 |
| A digital timer unit employs a capture register and a save register. The capture register latches count data provided from a counter in accordance with a first edge of an event pulse. The save register latches count data of the capture register in accordance with a second edge of the eve |
| 5206945 |
Single-chip pipeline processor for fetching/flushing instruction/data caches in response to firs |
April 27, 1993 |
| A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory, and an instruction controller reading out an instruction from the first as |
| 5200893 |
Computer aided text generation method and system |
April 6, 1993 |
| A computer aided text generation system and method provides functions of aiding a logical outline structure of a text, aiding the text generation using a conventional expression, aiding the text generation without using conventional expression, aiding the refinement of the generated text |
| 5197096 |
Switching method and apparatus having subscriber state management function |
March 23, 1993 |
| A switching system is provided in which when a calling subscriber has transmitted an identification (ID) number of a called subscriber and an ID number of the calling subscriber from a calling terminal to a switching equipment having a subscriber control table at the time of making a cal |
| 5193159 |
Microprocessor system |
March 9, 1993 |
| When a coprocessor communicates a plurality of data items with a master processor and a memory according to a bus access cycle activated by the master processor, the coprocessor is supplied therein with information indicating a data storage position as a data transfer source or desti |
| 5179694 |
Data processor in which external sync signal may be selectively inhibited |
January 12, 1993 |
| An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is |
| 5170474 |
Method of searching a queue in response to a search instruction |
December 8, 1992 |
| A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing is performed in response to an instruction based on an output from the decoder, the search instruction which identifies a d |
| 5159664 |
Graphic display apparatus |
October 27, 1992 |
| A graphic processor comprises an input device for inputting a command from an operator, a display device for displaying graphic data and a computer for preparing and correcting graphic data by a command input from the operator and for making display control of the display device. When th |
| 5148526 |
Data processing system with an enhanced cache memory control |
September 15, 1992 |
| A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) corresponds to an area (such as a status register in the above-mentioned micr |
