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Galileo Technologies Ltd. Patents
Assignee:
Galileo Technologies Ltd.
Address:
Mobile Post Misgav, IL
No. of patents:
7
Patents:












Patent Number Title Of Patent Date Issued
6240065 Bit clearing mechanism for an empty list May 29, 2001
A method and apparatus for managing packet memory is provided. The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity
5999981 Switching ethernet controller providing packet routing December 7, 1999
A switched Ethernet controller (SEC) device and associated method that provides processor based intervention in the packet routing decision process is provided. The method of routing a multicast packet between a source port on a source device and a plurality of destination ports on a
5930261 Bus protocol July 27, 1999
A write-only data transfer protocol for peripheral component interface busses and a method for transferring data between source and destination communication units is provided. The method includes the source communication unit writing a buffer allocation request to the destination un
5923660 Switching ethernet controller July 13, 1999
An Ethernet controller, for use within an Ethernet network of other Ethernet controller connected together by a bus, is provided. The Ethernet controller includes a plurality of ports including at least one bus port associated with ports connected to other switching Ethernet controllers,
5913042 Method and apparatus for managing packet memory June 15, 1999
A method and apparatus for managing packet memory is provided The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of
5841722 First-in, first-out (FIFO) buffer November 24, 1998
A variable sized FIFO buffer whose size changes in accordance with how much data is present to be passed between the two systems is provided.One embodiment of the FIFO buffer includes at least one lower FIFO, at least one upper FIFO, a RAM and a controller. The upper FIFO buffer receives
5809557 Memory array comprised of multiple FIFO devices September 15, 1998
A multiple FIFO array which does not use numerous single FIFO devices is provided. The multiple FIFO array includes a memory partitioned into a plurality of N sections, each section corresponding to one of N FIFOs. The memory has a write address input, write strobe input, data input, rea

 
 
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