| Patent Number |
Title Of Patent |
Date Issued |
| 7620760 |
Non-high impedence device and method for reducing energy consumption |
November 17, 2009 |
| A device that includes: a first bus, connected between a first logic and a first circuit; a group of second buses connected between the first logic and between multiple non-high impedance circuit access logics associated with multiple circuits; wherein each circuit access logic is adapte |
| 7619464 |
Current comparison based voltage bias generator for electronic data storage devices |
November 17, 2009 |
| An electronic data storage system uses current comparison to generate a voltage bias. In at least one embodiment, a voltage bias generator, that includes a current differential amplifier, generates a current that charges a load to a predetermined voltage bias level. The current compa |
| 7619440 |
Circuit having logic state retention during power-down and method therefor |
November 17, 2009 |
| A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled to the second con |
| 7619297 |
Electronic device including an inductor |
November 17, 2009 |
| An electronic device can include an inductor overlying a shock-absorbing layer. In one aspect, the electronic device can include a substrate, an interconnect level overlying the substrate, and the shock-absorbing layer overlying the interconnect level. The inductor can include conductive |
| 7619275 |
Process for forming an electronic device including discontinuous storage elements |
November 17, 2009 |
| A process for forming an electronic device can include forming a trench within a substrate, wherein the trench includes a wall and a bottom. The process can also include including forming a portion of discontinuous storage elements that lie within the trench, and forming a first gate |
| 7619273 |
Varactor |
November 17, 2009 |
| A varactor comprising a first layer separated from a second layer by an insulating layer, wherein the first layer is a first type of semiconductor material and the second layer is a second type of semiconductor material and the insulation layer is arranged to allow an accumulation re |
| 7619270 |
Electronic device including discontinuous storage elements |
November 17, 2009 |
| An electronic device can include discontinuous storage elements that lie within a trench. The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate. The electronic device can also include dis |
| 7618902 |
Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer |
November 17, 2009 |
| A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further i |
| 7617437 |
Error correction device and method thereof |
November 10, 2009 |
| A device for error correction includes a memory control module to disable error processing for a memory location depending on the state of a status indicator. The status indicator can be set so that error processing is disabled when valid error correction and detection information for th |
| 7616676 |
Method and system for performing distance measuring and direction finding using ultrawide bandwi |
November 10, 2009 |
| An identification tag is provided in which radio frequency (RF) circuitry and ultrawide bandwidth (UWB) circuitry are both provided on the same tag, along with some UWB-RF interface circuitry. The RF circuitry is used to detect when the identification tag must be accessed, and is used to |
| 7616509 |
Dynamic voltage adjustment for memory |
November 10, 2009 |
| A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the m |
| 7615866 |
Contact surrounded by passivation and polymide and method therefor |
November 10, 2009 |
| A semiconductor device has contact between the last interconnect layer and the bond pad that includes a barrier metal between the bond pad and the last interconnect layer. Both a passivation layer and a polyimide layer separate the last interconnect layer and the bond pad. The passivatio |
| 7615806 |
Method for forming a semiconductor structure and structure thereof |
November 10, 2009 |
| Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a |
| 7615318 |
Printing of design features using alternating PSM technology with double mask exposure strategy |
November 10, 2009 |
| For cases where one edge of a design feature is to be printed through a shifter mask and another one is to be printed through a binary trim mask, and where no upsizing can be performed due to the local density of the design, it is proposed to add shifters with respect to the shifter mask |
| 7613981 |
System and method for reducing power consumption in a low-density parity-check (LDPC) decoder |
November 3, 2009 |
| A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module checks whether a check node is in sleep mode. The check node is considered to be in sleep mo |
| 7613775 |
Network message filtering using hashing and pattern matching |
November 3, 2009 |
| Hashing and pattern matching are used in an information processing system to process incoming messages from a network such as an Ethernet-based network. Using hashing and pattern matching increases the efficiency of message acceptance and rejection without increasing software-based p |
| 7612619 |
Phase detector device and method thereof |
November 3, 2009 |
| A device and method for phase detection are disclosed. The device includes a phase differential module that provides a phase difference signal based on the phase difference between a data signal and a reference signal. The phase difference signal is provided to a first gate of a multi-ga |
| 7612613 |
Self regulating biasing circuit |
November 3, 2009 |
| A disclosed self regulating biasing circuit (SRBC) includes an unregulated node that couples to an unregulated power supply that produces a supply voltage. An impedance element of the SRBC carries an unregulated current having a nominal component and a variance component between an u |
| 7612588 |
Power on detection circuit |
November 3, 2009 |
| A power on detection circuit for accurately detecting an input voltage with a simple circuit structure and reduced current consumption includes a voltage conversion circuit, which converts input voltage into current, and a latch circuit, which holds the power on detection signal. The |
| 7612577 |
Speedpath repair in an integrated circuit |
November 3, 2009 |
| A circuit comprises a first plurality of transistors of a first channel length disposed along a speedpath, the first plurality of transistors providing a first timing performance. The circuit also comprises a second plurality of transistors of a second channel length having an expected |
| 7611955 |
Method of forming a bipolar transistor and semiconductor component thereof |
November 3, 2009 |
| A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; |
| 7611936 |
Method to control uniformity/composition of metal electrodes, silicides on topography and device |
November 3, 2009 |
| A method for depositing metals on surfaces is provided which comprises (a) providing a substrate (103) having a horizontal surface (107) and a vertical surface (105); (b) depositing a first metal layer (109) over the horizontal and vertical surfaces; (c) depositing a layer of polysilicon |
| 7610809 |
Differential capacitive sensor and method of making same |
November 3, 2009 |
| A differential capacitive sensor (50) includes a movable element (56) pivotable about a rotational axis (60). The movable element (56) includes first and second sections (94, 96). The first section (94) has an extended portion (98) distal from the rotational axis (60). A static layer |
| 7610466 |
Data processing system using independent memory and register operand size specifiers and method |
October 27, 2009 |
| Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate |
| 7609779 |
RF transmitter with interleaved IQ modulation |
October 27, 2009 |
| An RF modulator supporting wide-band signals includes IQ modulation by interleaving the in-phase and quadrature signals. The modulator can be implemented using an integrated circuit having a baseband in-phase stage that receives an in-phase analog input signal, a baseband quadrature |
| 7609541 |
Memory cells with lower power consumption during a write operation |
October 27, 2009 |
| A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node, an |
| 7608942 |
Power management system |
October 27, 2009 |
| An integrated circuit (103) having a plurality of integrated circuit portions (111, 113, and 115) where each of the plurality of integrated circuit portions receives a corresponding voltage of a plurality of voltages. Selection circuitry (127 and 123) selects a selected voltage of th |
| 7608913 |
Noise isolation between circuit blocks in an integrated circuit chip |
October 27, 2009 |
| An integrated circuit includes a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard reg |
| 7608908 |
Robust deep trench isolation |
October 27, 2009 |
| Higher voltage device isolation structures (40, 60, 70, 80, 90, 90') are provided for semiconductor integrated circuits having strongly doped buried layers (24, 24''). One or more dielectric lined deep isolation trenches (27, 27', 27'', 27''') separates adjacent device regions (411, |
| 7608898 |
One transistor DRAM cell structure |
October 27, 2009 |
| A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a |
| 7608893 |
Multi-channel transistor structure and method of making thereof |
October 27, 2009 |
| A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel |
| 7608513 |
Dual gate LDMOS device fabrication methods |
October 27, 2009 |
| An N-channel device (40, 60) is described having a lightly doped substrate (42, 42') in which adjacent or spaced-apart P (46, 46') and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42') and is spaced apart from the wells (46, |
| 7605652 |
Loop gain equalizer for RF power amplifier |
October 20, 2009 |
| The output power of an RF power amplifier is controlled using a feedback loop including a differential integrator for controlling the amplifier's bias voltage. The gain of integration in the differential integrator is varied so as to compensate for variations in the derivative of the pow |
| 7603902 |
Temperature compensation circuit, trimming circuit, and acceleration detector |
October 20, 2009 |
| A temperature compensation circuit having satisfactory linearity, a trimming circuit including a plurality of temperature gradients, and an acceleration detector having a wide applicable temperature range. A plurality of resistor elements R1 to R4, R5 to R8, R21 to R24, R25 to R28 ar |
| 7603094 |
DC offset correction for direct conversion receivers |
October 13, 2009 |
| A direct current (DC) offset correction system for a direct conversion receiver and corresponding receiver and methods facilitate reduction of DC offsets in such receivers. One method includes calibrating a DC offset correction system in a closed loop configuration over each of a plurali |
| 7602862 |
Mixing module and methods for use therewith |
October 13, 2009 |
| A mixing module includes a plurality of switched sample modules operably for generating a corresponding plurality of samples of an analog input signal in response to a control signal. A control module generates a mixing sequence and a control signal based on the mixing sequence, the |
| 7602861 |
Wireless receiver for removing direct current offset component |
October 13, 2009 |
| A wireless receiver includes a hardware (HW) block, a converter block and a digital signal processor (DSP). The HW block receives a wireless signal having a first DC Offset Component (DCOC), removes a portion of the first DCOC to produce a residual DCOC centered at DC, and generates para |
| 7602837 |
Beamforming for non-collaborative, space division multiple access systems |
October 13, 2009 |
| A wireless communication system noncollaborative, multiple input, multiple output (MIMO) space division multiple access (SDMA) system determines subscriber station combining and weighting vectors that yield a high average signal-to-interference plus noise ratio (SINR). Each subscriber |
| 7602233 |
Voltage multiplier with improved efficiency |
October 13, 2009 |
| A multi-stage voltage multiplication circuit and methodology are provided which use a multi-stage charge pump boosting circuit (210) and two-stage pass gate circuit (220) having complementary power switches (M6, M9, M7, M10) to efficiently develop an output voltage (V.sub.OUT) that is hi |
| 7602168 |
Voltage regulator for integrated circuits |
October 13, 2009 |
| A voltage regulator for a charge pump includes a capacitor divider and a reset circuit. The capacitor divider produces, based on an input voltage (VPP), a sample voltage at a sampling node. The sampling node and a reference voltage VREF are connected to respective inputs of a comparator |
| 7602014 |
Superjunction power MOSFET |
October 13, 2009 |
| An embodiment of an MOS device includes a semiconductor substrate of a first conductivity type, a first region of the first conductivity type having a length L.sub.acc and a net active dopant concentration of about N.sub.first, a pair of spaced-apart body regions of a second opposite |
| 7599432 |
Method and apparatus for dynamically inserting gain in an adaptive filter system |
October 6, 2009 |
| A method and apparatus for dynamically inserting gain in an adaptive filter is taught. This selective insertion of gain may be used to allow an adaptive filter to converge more quickly and/or to overcome inherent limitations of the adaptive filter. An echo canceller (e.g. 20 and 22 in |
| 7599321 |
Prioritization of connection identifiers for an uplink scheduler in a broadband wireless access |
October 6, 2009 |
| An uplink access method in a mobile subscriber station of a broadband wireless access communication system prioritizes uplink bandwidth allocation according to QoS types of requested service. A scheduling priority is assigned to each type of service flow to guarantee the highest data |
| 7599236 |
In-circuit Vt distribution bit counter for non-volatile memory devices |
October 6, 2009 |
| Integrated testing components and testing algorithm on a non-volatile memory module provide faster Vt (threshold voltage) distributions during the module verification process. The memory module includes address and voltage scanning components and a bit counter for storing the number of |
| 7598805 |
Load insensitive balanced power amplifier and related operating method |
October 6, 2009 |
| A balanced power amplifier that is insensitive to load line variations is provided. The balanced power amplifier is suitable for use in wireless transmitter applications, such as cellular telephones, mobile computing devices, and portable communication devices. An embodiment of such a |
| 7598784 |
System and method for controlling signal transitions |
October 6, 2009 |
| In accordance with the present disclosure, an electronic circuit of an integrated circuit is configured to receive an input signal that has a falling transition and a rising transition and provide a selectable delay of the input signal transitions on its output. The output of the dis |
| 7598716 |
Low pass filter low drop-out voltage regulator |
October 6, 2009 |
| A low dropout voltage regulator is described having a pass device, differential amplifiers, and a feedback loop including a low pass filter. Two differential amplifiers arranged in parallel coupled to the low pass filter in the feedback loop provide a specified and stable DC voltage |
| 7598596 |
Methods and apparatus for a dual-metal magnetic shield structure |
October 6, 2009 |
| A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or "MRAM") includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substan |
| 7598517 |
Superjunction trench device and method |
October 6, 2009 |
| Semiconductor structures and methods are provided for a semiconductor device (40) employing a superjunction structure (41) and overlying trench (91) with embedded control gate (48). The method comprises, forming (52-6, 52-9) interleaved first (70-1, 70-2, 70-3, 70-4, etc.) and second |
| 7596351 |
Audio system, radio record module and methods for use therewith |
September 29, 2009 |
| A radio record module includes a radio data system (RDS) decoder module, that decodes a received RDS signal, that has an associated audio signal, into received RDS data. A record module produces a digital data file from the digital audio signal in response to a record signal. A catalog |
