| Patent Number |
Title Of Patent |
Date Issued |
| 6470436 |
Eliminating memory fragmentation and garbage collection from the process of managing dynamically |
October 22, 2002 |
| A hardware or software apparatus, or a combination of both, is used for efficiently managing the dynamic allocation, access and release of memory used in a computational environment. This apparatus reduces, or preferably eliminates, the requirements for application housekeeping, such as |
| 6446188 |
Caching dynamically allocated objects |
September 3, 2002 |
| A system for mapping a sparsely populated virtual space of variable sized memory objects to a more densely populated physical address space of fixed size memory elements for use by a host processor comprises an object cache for caching frequently accessed memory elements and an object ma |
| 6426647 |
Dual rail drive for distributed logic |
July 30, 2002 |
| A logic circuit comprises a dual rail drive circuit having a first rail and a second rail. The logic circuit further comprises a logic block having a first input coupled to receive an input signal from the first rail of the dual rail driver, and a second input coupled to receive an input |
| 6378042 |
Caching associative memory |
April 23, 2002 |
| A system and method for operating an associative memory cache device in a computer system. The system comprises a search client configured to search for data in a caching associative memory such as a content addressable memory (CAM); a caching associative memory element coupled to the se |
| 6175514 |
Content addressable memory device |
January 16, 2001 |
| A content addressable memory device is provided which may include a novel CAM cell structure which reduces the total power dissipated by the CAM and improves the match time for the CAM. The novel CAM cell structure may include a CMOS implemented compare cell and a wide AND gate which com |
| 5999435 |
Content addressable memory device |
December 7, 1999 |
| A content addressable memory device is provided which may include a novel CAM cell structure which reduces the total power dissipated by the CAM and improves the match time for the CAM. The novel CAM cell stnictuire may include a CMOS implemented compare cell and a wide AND gate which co |
