| Patent Number |
Title Of Patent |
Date Issued |
| RE32200 |
MOS battery backup controller for microcomputer random access memory |
July 8, 1986 |
| MOS Control circuitry for incorporation on a microcomputer IC chip for assuring adequate power to maintain the data in an associated static random access memory. A rechargeable battery provides standby power, and the voltage level of the battery is compared with the microcomputer V.s |
| 7619480 |
Distributed class G type amplifier switching method |
November 17, 2009 |
| An improved Class G type amplifier is provided which switches between multiple power rails depending upon the instantaneous amplitude of the input signal versus the power rails without excessive distortion. The low voltage (inner) amplifier includes a plurality of parallel amplifier |
| 7619295 |
Pinched poly fuse |
November 17, 2009 |
| An electrical fuse has a region of a first conductivity type in a continuous type polysilicon of a second conductivity type that is opposite the first conductivity type. In one embodiment of the invention the PN junction between the region and the poly fuse is reverse biased. |
| 7618896 |
Semiconductor die package including multiple dies and a common node structure |
November 17, 2009 |
| A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input |
| 7618884 |
Method and device with durable contact on silicon carbide |
November 17, 2009 |
| A Schottky barrier silicon carbide device has a Re Schottky metal contact. The Re contact 27 is thicker than 250 Angstroms and may be between 2000 and 4000 Angstroms. A termination structure is provided by ion milling an annular region around the Schottky contact. |
| 7615982 |
Power converter able to rapidly respond to fast changes in load current |
November 10, 2009 |
| According to an embodiment, in a DC/DC converter delivering current to load, a method is provided for rapidly responding to changes in load current. The method includes: detecting fast changes in load current; and when a fast change in load current is detected, providing non-linear c |
| 7615978 |
Current mode control with feed-forward for power devices |
November 10, 2009 |
| A power device controller includes a voltage mode control loop to generate an error voltage and to control a power device and a current mode control loop to generate a current control voltage and to control the power device. The current mode control loop includes a current feed-forward t |
| 7608512 |
Integrated circuit structure with improved LDMOS design |
October 27, 2009 |
| A semiconductor integrated circuit including an LDMOS device structure comprises a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the semiconductor layer. First and second spaced-apart source regions of a first conductivity type are |
| 7602017 |
Short channel LV, MV, and HV CMOS devices |
October 13, 2009 |
| Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conduct |
| 7598144 |
Method for forming inter-poly dielectric in shielded gate field effect transistor |
October 6, 2009 |
| A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of thermal oxide and a laye |
| 7595683 |
Low-input-voltage charge pump |
September 29, 2009 |
| In one embodiment, a charge pump system includes an input terminal at which an input voltage is received, and an output terminal at which at an output voltage is provided. N stages are connected in cascade between the input terminal and the output terminal. Each of the N stages includes |
| 7595542 |
Periphery design for charge balance power devices |
September 29, 2009 |
| A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active are |
| 7595524 |
Power device with trenches having wider upper portion than lower portion |
September 29, 2009 |
| A field effect transistor includes a plurality of trenches extending into a silicon layer. Each trench has upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper |
| 7592668 |
Charge balance techniques for power devices |
September 22, 2009 |
| A charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current when biased in a conducting state. A non-active perimeter region surrounds the active area, wherein no current flows through the non-active perimeter when the |
| 7589338 |
Semiconductor die packages suitable for optoelectronic applications having clip attach structure |
September 15, 2009 |
| An optocoupler package is disclosed. The package includes a substrate comprising a substrate surface, a first device, and a clip structure attached to the first device. The clip structure and the first device are mounted on the substrate, and the first device is oriented at an angle |
| 7586179 |
Wireless semiconductor package for efficient heat dissipation |
September 8, 2009 |
| Disclosed in this specification is a wireless semiconductor package with multiple dies, at least two of which are attached to a thermally and electrically conductive heat sink. The package provides an efficient means for dissipating heat. |
| 7586178 |
Alternative flip chip in leaded molded package design and method for manufacture |
September 8, 2009 |
| A semiconductor package is disclosed. The package includes a leadframe structure comprising a die attach region and plurality of leads. A molding material is molded around at least a portion of the leadframe structure, and comprises a window. A semiconductor die comprising an edge is |
| 7586156 |
Wide bandgap device in parallel with a device that has a lower avalanche breakdown voltage and a |
September 8, 2009 |
| A wide bandgap device in parallel with a device having a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device. |
| 7582956 |
Flip chip in leaded molded package and method of manufacture thereof |
September 1, 2009 |
| A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate t |
| 7582519 |
Method of forming a trench structure having one or more diodes embedded therein adjacent a PN ju |
September 1, 2009 |
| A semiconductor structure is formed as follows. A semiconductor region is formed to have a P-type region and a N-type region forming a PN junction therebetween. A first trench is formed extending in the semiconductor region adjacent at least one of the P-type and N-type regions is formed |
| 7576446 |
Zero voltage switching (ZVS) in a power converter |
August 18, 2009 |
| In one embodiment, a power converter includes a first switch in a main power loop for delivering power to a first load. A second switch in an auxiliary power loop delivers power to a second load. The power converter system further includes means for providing zero voltage switching (ZVS) |
| 7576429 |
Packaged semiconductor device with dual exposed surfaces and method of manufacturing |
August 18, 2009 |
| The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The |
| 7576388 |
Trench-gate LDMOS structures |
August 18, 2009 |
| MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetr |
| 7566931 |
Monolithically-integrated buck converter |
July 28, 2009 |
| An integrated buck converter is formed on a substrate of a first polarity type and having a first and second substrate surface. An epitaxial layer is formed over the first substrate surface and has a first epitaxial layer surface. A drift region lightly-doped with dopants of a second |
| 7564124 |
Semiconductor die package including stacked dice and heat sink structures |
July 21, 2009 |
| A semiconductor package including stacked packages is disclosed. The semiconductor die package includes a first heat sink structure, a first semiconductor die attached to the first heat sink structure and having a first exterior surface, an intermediate conductive element attached to |
| 7564096 |
Scalable power field effect transistor with improved heavy body structure and method of manufact |
July 21, 2009 |
| A field effect transistor (FET) includes a semiconductor region of a first conductivity type and a well region of a second conductivity type extending over the semiconductor region. A gate electrode is adjacent to but insulated from the well region, and a source region of the first c |
| 7560787 |
Trench field plate termination for power devices |
July 14, 2009 |
| In accordance with an embodiment of the invention, a semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. A first silicon region o |
| 7560311 |
Robust leaded molded packages and methods for forming the same |
July 14, 2009 |
| A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in |
| 7554407 |
Multi-mode power amplifier with low gain variation over temperature |
June 30, 2009 |
| A multi-mode RF amplifier is described having at least a higher and a lower power path coupling an input to an output. At a pre-selected output power level, the higher power path is enabled while the lower power path is disabled when more output power is required. The process is reversed |
| 7554382 |
Method for reducing insertion loss and providing power down protection for MOSFET switches |
June 30, 2009 |
| An FET switch comprising a single or parallel opposite polarity FETS is illustrated with wells that are driven from internal power rails. The internal power rails are logically coupled by other driving FET switches to, in one case, the higher of a positive power supply or signal level |
| 7553740 |
Structure and method for forming a minimum pitch trench-gate FET with heavy body region |
June 30, 2009 |
| A field effect transistor is formed as follows. Openings are formed in a masking layer extending over a surface of a silicon region. A trench is formed in the silicon region through each opening in the masking layer. A layer of silicon is formed along sidewalls and bottom of each trench |
| 7551007 |
Partial switch gate driver |
June 23, 2009 |
| A power switch driver includes a top driver switch, a bottom driver switch, a driver node between them, and driver logic. The power switch driver can turn on the power switch by controlling a gate voltage of the power switch to a first voltage level and to turn off the power switch by |
| 7544571 |
Trench gate FET with self-aligned features |
June 9, 2009 |
| A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. A gate electrode recessed in each trench is formed. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by imp |
| 7538614 |
Differential amplifier with independent output common mode adjustment |
May 26, 2009 |
| A fully differential amplifier with a high common mode rejection ratio with an independent output voltage setting is disclosed. The amplifier may be arranged with a single ended output or a differential output. The gain may be set by adjusting a resistor without affecting bandwidth of |
| 7538583 |
High voltage integrated circuit driver with a high voltage PMOS bootstrap diode emulator |
May 26, 2009 |
| A high voltage circuit driver includes high and low side driver cells to drive a high and a low side power MOSFET, a bootstrap circuit to energize the high side driver cell, a high voltage PMOS transistor (HVPMOS) between a voltage source and the bootstrap circuit, wherein the HVPMOS is |
| 7537958 |
High performance multi-chip flip chip package |
May 26, 2009 |
| A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separ |
| 7535309 |
Low power, temperature and frequency, tunable, on-chip clock generator |
May 19, 2009 |
| A tunable, low power clock generator employs a voltage regulator, one or current generators and a variable resistor bank that, together, produce a control voltage for trimming a VCO. The control voltage is arranged to also compensate, at least, for the variables of temperature, supply |
| 7534683 |
Method of making a MOS-gated transistor with reduced miller capacitance |
May 19, 2009 |
| A trench MOS-gated transistor is formed as follows. A first region of a first conductivity type is provided. A well region of a second conductivity type is then formed in an upper portion of the first region. A trench is formed which extends through the well region and terminates wit |
| 7531888 |
Integrated latch-up free insulated gate bipolar transistor |
May 12, 2009 |
| A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conduc |
| 7529105 |
Configuring a power converter to operate with or without burst mode functionality |
May 5, 2009 |
| In one embodiment, a method is provided for a power converter system. The method includes: automatically configuring the power converter system to operate with burst mode functionality if a control module of the power converter system is coupled in a first arrangement; and automatically |
| 7525259 |
Primary side regulated power supply system with constant current output |
April 28, 2009 |
| According to an embodiment, a power supply system has a primary side and a secondary side. An input terminal on the primary side is operable to receive an input voltage. An output terminal on the secondary side is operable to be connected to a load for providing current thereto. Circ |
| 7525179 |
Lead frame structure with aperture or groove for flip chip in a leaded molded package |
April 28, 2009 |
| A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die a |
| 7522433 |
Efficient voltage rail generation |
April 21, 2009 |
| A voltage reference generation circuit having switch pairs coupled to systematically commutate a flying capacitor among adjacent pairs of voltage rail outputs. The circuit requires only a single flying capacitor, N+1 switch pairs, and N storage capacitors, to generate N intermediate |
| 7521773 |
Power device with improved edge termination |
April 21, 2009 |
| A field effect transistor includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the te |
| 7518895 |
High-efficiency power converter system |
April 14, 2009 |
| In one embodiment, a power converter system includes a first input terminal and a second input terminal operable to connect to an alternating current (AC) power source, and an output terminal at which an output voltage can be provided to a load. A first inductor and a first diode are |
| 7518446 |
Multi-mode power amplifier with reduced low power current consumption |
April 14, 2009 |
| A multi-mode RF amplifier is disclosed having high and low output power modes composed of two power paths. When the multi-mode RF amplifier is biased into the high power, HP, mode, substantial power is delivered via both (first and second) paths. While in the low power, LP, mode, power i |
| 7514983 |
Over-voltage tolerant pass-gate |
April 7, 2009 |
| A pass-gate having a single or parallel opposite polarity FETs is disclosed. The wells of the primary transistor switches are driven from circuitry that reduces over-voltage leakage and other malfunctions. A circuit that drives the wells is also used to power enable circuits that dri |
| 7514322 |
Shielded gate field effect transistor |
April 7, 2009 |
| A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first con |
| 7511339 |
Field effect transistor and method of its manufacture |
March 31, 2009 |
| A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body position |
| 7504691 |
Power trench MOSFETs having SiGe/Si channel structure |
March 17, 2009 |
| Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces p |
