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Fairchild Camera and Instrument Corporation Patents
Fairchild Camera and Instrument Corporation
Mountain View, CA
No. of patents:

1 2 3 4

Patent Number Title Of Patent Date Issued
D252499 Clock July 31, 1979
D247755 Video game console April 18, 1978
D247754 Hand-held controller for a video game or the like April 18, 1978
D245898 Casing for an electronic wristwatch or the like September 27, 1977
4920071 High temperature interconnect system for an integrated circuit April 24, 1990
A semiconductor integrated circuit device is provided with an electrical interconnect system which is stable at high temperatures. The interconnect system employs refractory metal compounds which are electrically conductive, which form stable couples with silicon and compounds thereof,
4912344 TTL output stage having auxiliary drive to pull-down transistor March 27, 1990
A novel output stage is provided for producing a TTL output signal in response to the differential output signals from an ECL switch. The output stage includes a translator portion to shift the levels of the complementary signals produced by the ECL switch to the appropriate levels f
4888300 Submerged wall isolation of silicon islands December 19, 1989
To completely isolate an island of silicon, a trench is cut into an epitaxial layer to provide access to a differently doped buried layer. While suspending the portion of the epitaxial layer surrounded by the trench by means of an oxide bridge, the underlying region of the buried lay
4864228 Electron beam test probe for integrated circuit testing September 5, 1989
An improved electron beam test probe apparatus and a method for use of said apparatus for use in measuring the potential in a specimen which enables measurements to be insensitive to local electric fields in the vicinity of the point at which the potential of the specimen is being measur
4796080 Semiconductor chip package configuration and method for facilitating its testing and mounting on January 3, 1989
A semiconductor chip package configuration and a method are disclosed for facilitating testing of the chip package and mounting of the chip package on a substrate by forming one or more lead alignment bars in interconnecting relation with adjacent leads on the chip package, the lead
4747072 Pattern addressable memory May 24, 1988
A memory system for storing and retrieving data sequences of symbols in response to a query sequence is disclosed. Each of the sequences is made up of three types of symbols, constants, delimiters, and variables. A data sequence is retrieved in response to a query sequence if the two seq
4744059 Apparatus and method for reducing write recovery time in a random access memory May 10, 1988
An apparatus for reducing the write recovery time of a memory during a write operation is responsive to the detection of a write enable signal for causing the data being written into a selected memory cell to be immediately coupled out on the memory's corresponding output data line i
4706019 Electron beam test probe system for analyzing integrated circuits November 10, 1987
An electron beam test probe system for analyzing the operation of an integrated circuit is described. It includes a circuit for generating a test signal pattern and coupling the test signal pattern to the integrated circuit under test. It also includes an electron beam test probe for
4675549 Black and white reference and end-of-scan indicator for charge coupled devices June 23, 1987
Structure is disclosed for a charge-coupled device for generating reference signals indicative of black and white optical conditions and for generating an end-of-scan indicator signal. The black reference signal is generated by electrically and optically isolating one or more photosites
4658372 Scale-space filtering April 14, 1987
Information indicative discrete events of interest imbedded in raw data are globally classified, or filtered with respect to scale and changes in the scale of observation to effect intelligent perception of phenomena. Large scale components are classified as events while small scale comp
4627034 Memory cell power scavenging apparatus and method December 2, 1986
The present invention utilizes the power available for application to a static RAM cell in a manner which provides efficient use of the power so that greater standby power may be applied to the static RAM to increase the memory speed. The current required to maintain the memory cell in a
4611123 High voltage analog solid state switch September 9, 1986
A high voltage analog solid state switch is disclosed which includes a pair of MOS FET's 10 and 20 having commonly coupled sources 11 and 21 and commonly coupled gates 13 and 23. A photovoltaic generator 30 and an opto-coupler 40 are connected in parallel between the commonly coupled
4594544 Participate register for parallel loading pin-oriented registers in test equipment June 10, 1986
An automatic test system for parallel loading of data into pin registers 100 associated with pins of a device being tested includes data bus 130 for transmitting data; an address bus 120 for transmitting addresses; a set of pin registers 100, each having a unique address and each coupled
4583075 Method and apparatus for analyzing an analog-to-digital converter with a nonideal digital-to-ana April 15, 1986
A method for statistically calibrating an analog-to-digital converter with an electronic test system. A digital-to-analog converter which has been calibrated by premeasured weighting coefficients with respect to two-state orthogonal signals is excited with two state signals at each input
4572971 Tri-state driver circuit for automatic test equipment February 25, 1986
A tri-state driver circuit 10 for selectively driving a node of a device under test by applying and switching between two reference voltages, and for selectively operating at a high impedance output state. Two current sources 16 and 18 provide a bridge current that flows through a diode
4550405 Deskew circuit for automatic test equipment October 29, 1985
An electrical pulse edge timing adjustment circuit 10 comprising one or more deskew elements 5. In each deskew element, a pulse train is passed through an inverter 20. The falling rate of pulse edges on the inverter output line 21 is controlled by a capacitor 24 and an adjustable current
4543595 Bipolar memory cell September 24, 1985
A bipolar memory cell is fabricated by forming diodes 60 and 65 on top of the transistors Q1 and Q2 formed in the underlying substrate 10. Metal silicide 30 overlies strips 34 and 35 of doped polycrystalline silicon 25, 28, 37, and 38 to cross-couple the bases and collectors of the two
4542037 Laser induced flow of glass bonded materials September 17, 1985
A tunable CO.sub.2 gas laser is used to selectively heat various SiO.sub.2 -based materials to elevated temperatures while maintaining an active device region at relatively low temperatures, to, for example, induce densification and/or flow of the SiO.sub.2 -based material to round off
4536844 Method and apparatus for simulating aural response information August 20, 1985
Speech and like signals are analyzed based on a model of the function of the human hearing system. The model of the inner ear is expressed as signal processing operations which map acoustic signals into neural representations. Specifically, a high order transfer function is modeled a
4527907 Method and apparatus for measuring the settling time of an analog signal July 9, 1985
Method and apparatus are provided for measuring the settling time, relative to a reference time, of an analog signal having a varying amplitude. The apparatus includes a pair of comparators U1 and U2 for comparing the amplitude of the analog signal with first and second reference signals
4523143 Digital logic level comparator particularly for digital test systems June 11, 1985
A digital comparator for determining whether a digital test signal qualifies as an expected logic level, particularly suited to in-circuit digital testing applications. First and second comparing circuits, each formed by a differential amplifier circuit, receive the test signal, a hi
4517511 Current probe signal processing circuit employing sample and hold technique to locate circuit fa May 14, 1985
During the in-circuit testing of electronic components, stimulus pulses are applied to a circuit bus producing an improper output signal, and the response of the circuit at various nodes connected to the bus is sensed with a current probe. An output signal from the current probe that is
4511846 Deskewing time-critical signals in automatic test equipment April 16, 1985
Apparatus is provided for supplying deskewed signals. The apparatus includes a timing generator (20) for generating a pulse of desired duration, a deskew unit (17) connected to receive a pulse and adjust its width to compensate for previous errors, a differentiation network (15) for
4502127 Test system memory architecture for passing parameters and testing dynamic components February 26, 1985
A test system memory architecture for passing parameters and testing dynamic components includes a main memory 15, a mask memory 20, and a definition memory 25, operating under control of a main sequence control memory 18. A corresponding subroutine memory 38, subroutine mask memory
4495382 Telephone regulator circuitry January 22, 1985
This invention provides a single integrated circuit device which replaces the non-integrated "encapsulated circuit" of the standard prior art telephone set. The circuit of this invention achieves proper D.C. regulation of the telephone line, by presenting one of several possible D.C.
4472873 Method for forming submicron bipolar transistors without epitaxial growth and the resulting stru September 25, 1984
A vertical bipolar transistor is fabricated in a semiconductor substrate without an epitaxial layer using oxide isolation and ion implantation techniques. Ion implantation energies in the KEV ranges are used to implant selected ions into the substrate to form a collector region and b
4455325 Method of inducing flow or densification of phosphosilicate glass for integrated circuits June 19, 1984
Phosphorus-doped silicon oxide glass is flowed on an integrated circuit by raising the pressure in which that integrated circuit is placed above atmospheric for a selected period of time and heating said phosphosilicate glass to a selected temperature sufficient to cause said glass to fl
4451971 Lift-off wafer processing June 5, 1984
An improved lift-off process for forming metallized interconnections between various regions on a semi-conductor device relies on the use of a particular polyimide in forming a protective mask over the device. The polyimide is a copolymer of an aromatic cycloaliphatic diamine and a d
4435790 High speed, nonvolatile, electrically erasable memory cell and system March 6, 1984
A method for encoding binary data into an electrically erasable memory. The memory includes a matrix of memory cells formed as a plurality of rows (X write lines/X sense lines/source lines) and columns (Y sense lines) with each cell including a floating gate field effect PMOS transistor
4435786 Self-refreshing memory cell March 6, 1984
A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the drain of said second transistor
4434347 Lead frame wire bonding by preheating February 28, 1984
In a method for welding a lead wire or bonding wire from a microcircuit chip mounted on a lead frame to a lead frame finger, the lead frame finger is preheated prior to any substantial electrical or thermal coupling between the lead frame finger and chip. Intense but controlled energy is
4433414 Digital tester local memory data storage system February 21, 1984
In a digital tester for evaluating electronic components, a local memory unit for each data channel in the tester is loaded with test vector information only in the locations of the memory relating to transitions that take place in the operation of the data channel. In addition, a tr
4428796 Adhesion bond-breaking of lift-off regions on semiconductor structures January 31, 1984
A process is described for removing polyimide regions adhered to the surface of a semiconductor structure 10 which includes the steps of heating the structure 10 and the polyimide regions 12 to between and C., immersing the structure in a solution of one of me
4420497 Method of detecting and repairing latent defects in a semiconductor dielectric layer December 13, 1983
Defects in dielectric layers exhibiting low dielectric strength on silicon substrates (11) are deliberately damaged during manufacture to allow their repair by the formation of dielectric plugs (13B). The defects are damaged by the application of an electric field, and are repaired by th
4420365 Formation of patterned film over semiconductor structure December 13, 1983
A novel process is disclosed for the selective etching of a protective layer over a substrate according to a predetermined pattern, which does not involve the use of chemical vapor deposition or vacuum techniques. The process incorporates the techniques of electroless metal deposition af
4417914 Method for forming a low temperature binary glass November 29, 1983
The method of the invention provides a thin film deposit of a binary glass for use in integrated circuits which binary glass has a softening or flow point far below temperatures at which glasses normally used in connection with integrated circuits flow. After the binary glass has been de
4415794 Laser scanning method for annealing, glass flow and related processes November 15, 1983
A method for scanning the top surface of a semiconductor wafer prevents damage to the wafer (11) by ensuring that the laser beam (13) does not cross over the edge (11a) of the wafer during the scanning process nor approach within one (1) to two (2) millimeters to the edge of the wafer.
4370737 Sense amplifier and sensing methods January 25, 1983
A sense amplifier for determining the binary logic state of a dynamic memory cell (11.sub.x,y) preamplifies an initial voltage difference established between a first input line (17.sub.y) coupled to the memory cell (11.sub.x,y) and a first reference line (18.sub.y) coupled to a refer
4354257 Sense amplifier for CCD memory October 12, 1982
A sense amplifier for use with a charge coupled device in which capacitive coupled charge is employed with a flip-flop circuit to accelerate sense and readout. Operation of the amplifier is effected with two external clocks and two internally generated clocks.
4331452 Apparatus for crystal shaping May 25, 1982
In the present invention, a length of elongated single crystal ingot is mounted adjacent its ends and is ground while being rotated to provide a cylindrical shape. While still mounted, the crystal is rotated into a position to be x-rayed for the grinding of a flat thereon with the crysta
4330723 Transistor logic output device for diversion of Miller current May 18, 1982
A transistor logic output device is provided with an active element discharging transistor coupled between the base of the pulldown element transistor and ground or low potential for actively controlling a route to ground or low potential for diverting and discharging the so-called c
4321490 Transistor logic output for reduced power consumption and increased speed during low to high tra March 23, 1982
In a transistor logic output device the improvement comprising an active element discharging transistor coupled between the base of the pulldown element transistor and ground or low potential for actively controlling a route to ground or low potential for diverting and discharging so-cal
4277882 Method of producing a metal-semiconductor field-effect transistor July 14, 1981
A metal-semiconductor field-effect transistor is formed by providing a blanket layer of the same conductivity type as the semiconductor body, with field oxide subsequently being grown, and with a region of opposite conductivity type being formed to extend partially under the field oxide,
4251317 Method of preventing etch masking during wafer etching February 17, 1981
As a cassette holding wafers in an etchant bath is rotated, nitrogen gas is bubbled through the cassette adjacent the wafers to agitate the wafers, so as to ensure that etchant reaches all edge portions of the wafers.
4251300 Method for forming shaped buried layers in semiconductor devices utilizing etching, epitaxial de February 17, 1981
A method for forming a shaped buried layer in a semiconductor structure includes the steps of removing a portion of semiconductor material from adjacent the surface of the semiconductor substrate to form an indentation, introducing a dopant into the surface of the indentation to form
4230985 Fixturing system October 28, 1980
A fixturing system including a product access unit, receiver and support bracket. The product access unit has a top plate upon which the product under test is placed, which top plate is movable so as to carry the product under test into contact with a field of test probes. The product
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