| Patent Number |
Title Of Patent |
Date Issued |
| 7459951 |
Self-calibrating digital pulse-width modulator (DPWM) |
December 2, 2008 |
| A hybrid digital pulse width modulator can have a delay line with digitally programmable delay cells. The digitally programmable delay cells can be adjusted by a digital correction signal from a delay matching circuit. |
| 7457335 |
Fast loop laser diode driver |
November 25, 2008 |
| A laser diode driver circuit can comprise fast loop portion and a closed-loop portion. The closed-loop driver portion can provide a part of the current for a laser diode. The closed-loop drive portion output can be independent of a photodetector. The fast-loop driver portion can prov |
| 7441039 |
Method and apparatus for adapting mac and network processor core to packet format changes and fo |
October 21, 2008 |
| A data communications device that can operate in accordance with two or more protocols having different data formats and error-protection schemes. The protocol-dependent aspects of the device are handled by a peripheral portion of the device, allowing a substantially protocol-indepen |
| 7436245 |
Variable sub-bandgap reference voltage generator |
October 14, 2008 |
| A sub-bandgap reference voltage generator, generates a pair of variable voltages one having a positive temperature coefficient and one having a negative voltage coefficient. The pair of voltages are added to generate an output voltage whose value and temperature may be varied. To achieve |
| 7411460 |
Elimination of dummy detector on optical detectors using input common mode feedback |
August 12, 2008 |
| A voltage reference forces a constant voltage at the inputs to an amplifier, thereby negating a need for a dummy detector on the non-active input of the amplifier. |
| 7411426 |
Phase detector for RZ |
August 12, 2008 |
| A phase detector is adapted to receive first and second signals and generate third and fourth signals representative of the difference between the phases of the first and second signals. The phase detector assert the third signal in response to the assertion of the first signal and u |
| 7405689 |
Predictive analog to digital converters and methods of using |
July 29, 2008 |
| Methods and devices perform analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. A predictive guess is supplied as a |
| 7330056 |
Low power CMOS LVDS driver |
February 12, 2008 |
| A low voltage CMOS output driver is adapted to generate an output voltage that stays within predefined limits at relatively low supply voltages. The output driver includes, in part, a voltage-controlled resistor, a voltage-controlled current sink, and a switching stage. A control circuit |
| 7315210 |
Differential operational amplifier |
January 1, 2008 |
| The input stage of an operational amplifier includes at least four signal-receiving stages adapted to receive four primary input signals. If the voltage level associated with any of the input signal changes, at least one transistor in each of the at least four signal-receiving stages |
| 7292603 |
Memory-efficient conversion between differing data transport formats of SONET overhead data |
November 6, 2007 |
| In a SONET apparatus, the data flow differences between OC-768 and OC-192 can be exploited to effectuate conversion between OC-768 and OC-192 using as little as 256 bytes of memory. |
| 7242235 |
Dual data rate flip-flop |
July 10, 2007 |
| A flip-flop is configured to operate either in a double data-rate mode or a normal mode. When configured to operate in the double data-rate mode, the flip-flop outputs data on both edges of the applied clock. When configured to operate in the normal mode, the flip-flop outputs data on |
| 7199616 |
Method and apparatus to generate break before make signals for high speed TTL driver |
April 3, 2007 |
| A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in the driver. The no |
| 7127021 |
Interleaved pulse-extended phase detector |
October 24, 2006 |
| A mechanism for dealing with faster clock speeds by increasing the pulse width of the pump-up and pump-down pulses of a Hogge-type phase detector without dividing the clock. In particular, the NRZ data stream is divided into two, interleaved data streams which are provided through two se |
| 7113040 |
Differential amplifier |
September 26, 2006 |
| The input stage of an operational amplifier includes at least four signal-receiving stages adapted to receive four input signals. If the voltage level associated with any of the input signal changes, at least one transistor in each of the at least four signal-receiving stages conduct |
| 7109904 |
High speed differential resistive voltage digital-to-analog converter |
September 19, 2006 |
| A differential digital-to-analog voltage converter (VDAC) includes, in part, a resistor, and at least two decoding stages. The resistor is divided into N equal segments each disposed in a different one of N decoders forming a first decoding stage. The resistor segment in each decoder |
| 7102393 |
Detection of a closed loop voltage |
September 5, 2006 |
| To detect whether a closed-loop's voltage is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that dr |
| 7091754 |
CMOS LvPECL driver with output level control |
August 15, 2006 |
| A differential output driver includes an output block, a replication block, and a feedback control block. Each of the output and replication blocks further includes a preamplifier and a source-follower stage. The preamplifier of the output block receives a differential input voltage |
| 7078958 |
CMOS bandgap reference with low voltage operation |
July 18, 2006 |
| A bandgap reference voltage generator includes, in part, a first closed-loop circuit having a first operational amplifier and adapted to generate a first current with a positive temperature coefficient and a second closed-loop circuit having a second operational amplifier and adapted |
| 7057241 |
Reverse-biased P/N wells isolating a CMOS inductor from the substrate |
June 6, 2006 |
| A double well structure beneath an inductor to isolate it from the substrate. Contacts are provided for the deeper well and the substrate, to reverse bias the junction between the substrate and the deep well. In one embodiment, for a P-substrate, the deep well is an N-well, and the o |
| 7038720 |
Pixel-by-pixel digital control of gain and offset correction for video imaging |
May 2, 2006 |
| A method and apparatus for adjusting, on a pixel-by-pixel basis, the gain and offset in an AFE as the pixels are sequentially processed. Although the method can be used for any purpose, it is directed in particular to light source non-linearity, such as edge effects of a scanner. A uniqu |
| 7012794 |
CMOS analog switch with auto over-voltage turn-off |
March 14, 2006 |
| An analog transfer gate that can be connected to an external line of a chip that is also connected to a digital circuit. The transfer gate includes both NMOS and PMOS transistors for passing the analog signals in both directions. A voltage sensing circuit is connected to the external |
| 7000158 |
Simplifying verification of an SFI converter by data format adjustment |
February 14, 2006 |
| The present invention enables interface conversion verification with a single chip and improves problem isolation. Exemplary embodiments of the present invention can provide this by modifying the input data pattern (e.g., creating a 40G, or pseudo OC-768, frame by multiplexing four O |
| 6965606 |
Method and apparatus for byte rotation |
November 15, 2005 |
| A scheme is described for distributing data operations on an irregular data stream over multiple stages of a data aligner to generate a regular data stream having continuous filled byte positions. In one particular embodiment, data alignment may involve the prediction of a rotation amoun |
| 6960942 |
High speed phase selector |
November 1, 2005 |
| Method and circuitry for selecting phases while avoiding glitches in the output signal during phase switching. An integrated circuit having a plurality of input terminals coupled to receive a respective plurality of clock signals having different phases, and a plurality of control te |
| 6952240 |
Image sampling circuit with a blank reference combined with the video input |
October 4, 2005 |
| A programmable gain amplifier having three separately programmable amplifiers. A programmable transconductance amplifier is followed by a programmable transimpedance amplifier, then a programmable switched capacitor amplifier. In one embodiment, this programmable gain amplifier is im |
| 6947999 |
UART with compressed user accessible interrupt codes |
September 20, 2005 |
| An improved UART which has a number of channels, with each channel having a set of channel configuration registers. Each channel configuration register includes an interrupt source register. The interrupt source register has a multi-bit interrupt source code which is used to indicate |
| 6906593 |
Frequency compensation of wide-band resistive gain amplifier |
June 14, 2005 |
| A technique for minimizing the effect of parasitic capacitance in a resistive gain amplifier. Instead of the resistors being formed directly over the substrate, or over an oxide of the substrate, a semiconductor element (e.g., an n-well) is used between the resistor and the substrate. |
| 6865626 |
UART automatic half-duplex direction control with programmable delay |
March 8, 2005 |
| A UART with a FIFO buffer is provided. A circuit detects a last word transmitted from the FIFO buffer. A transmitter empty circuit generates a transmitter empty signal (RTS) when the last word transmitted from the FIFO buffer is detected. A delay circuit delays generation of the RTS |
| 6798857 |
Clock recovery circuit |
September 28, 2004 |
| A clock recovery circuit which has a transition detector connected to the incoming data stream. An output of the transition detector is connected to a gate, such as a D flip-flop, which has an input receiving the recovered clock. A zero or one output will be generated depending upon whet |
| 6774942 |
Black level offset calibration system for CCD image digitizer |
August 10, 2004 |
| An improved offset correction circuit for an image digitizing system having a correlated double sample and hold circuit, a programmable gain amplifier and an analog-to-digital converter. The output of the analog-to-digital converter is provided to a dual offset correction circuit. The du |
| 6754839 |
UART clock wake-up sequence |
June 22, 2004 |
| A UART with a clock oscillator that has a sleep mode. A counter is connected to the output of the clock oscillator. When the clock oscillator is awakened, the counter counts up to a specified count. Upon reaching the specified count, the output of the counter is enabled, which is connect |
| 6747503 |
CMOS transmission gate with high impedance at power off |
June 8, 2004 |
| A transmission gate circuit with high impedance during power off conditions, which includes a first transistor coupled between a first terminal and a second terminal and a second transistor coupled between the first terminal and the second terminal. Also included is a control circuit |
| 6744292 |
Loop filter capacitor multiplication in a charge pump circuit |
June 1, 2004 |
| A charge pump circuit with a small loop filter capacitor is disclosed in the invention. This is accomplished by providing multiple currents which add to the desired current, I. A switching circuit switches one of the currents through the capacitor, while directing a combination of the |
| 6717783 |
Short circuit power limiter |
April 6, 2004 |
| The present invention provides a short circuit power limiter circuit having a current sensor and a power limiter. The short circuit sensor sends a short circuit flag signal to the power limiter when the short circuit sensor detects a short circuit condition in a target circuit. The power |
| 6700431 |
I/O pad overvoltage protection circuitry |
March 2, 2004 |
| A protection circuit for a transmission gate having a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad. Biasing transistors are coupled to gates of the NMOS and PMOS transmission gate transistors to turn them on duri |
| 6693783 |
Bounce tolerant fuse trimming circuit with controlled timing |
February 17, 2004 |
| A method and apparatus for implementing trimming circuits. More particularly, embodiments of the present invention provide a transistor that supplies sufficient current to trim a trimming fuse when the transistor is powered up and after it receives a select signal at its gate. When t |
| 6683473 |
Input termination with high impedance at power off |
January 27, 2004 |
| An input termination circuit with high impedance at power off, which includes a first transistor coupled between a first terminal and a second terminal. The input termination circuit also includes a control circuit that monitors voltages on the first and second terminals and a first |
| 6680605 |
Single-seed wide-swing current mirror |
January 20, 2004 |
| A current mirror circuit that uses only a single seed current, and thus only a single current source. A transistor biasing circuit is connected in between the single current source and the two transistors of the first leg of the current mirror. The transistor biasing circuit provides two |
| 6624671 |
Wide-band replica output current sensing circuit |
September 23, 2003 |
| An indirect current sensing circuit and method for replicating an output current is disclosed. The present invention is capable of preventing device damage and circuit disruption by maintaining output voltage signal integrity and consuming negligible power as well as optimizing output |
| 6597222 |
Power down circuit for high output impedance state of I/O driver |
July 22, 2003 |
| A circuit for putting an output driver into a high impedance state upon failure of the power supply. This is accomplished by providing a first transistor that is connected between the power supply and the n-well to charge the n-well node of the PMOS drive transistor. Upon failure of the |
| 6573784 |
Low power wide bandwidth programmable gain CDS amplifier/instrumentation amplifier |
June 3, 2003 |
| A method and circuitry for implementing programmable gain. More particularly, embodiments of the present invention provide an amplifier circuit which can be used as a CDS-amp or an instrumentation amplifier. Included is a two-stage amplifier, each stage having a few as one transistor |
| 6501320 |
Self-powered, maximum-conductive, low turn-on voltage CMOS rectifier |
December 31, 2002 |
| A rectifier circuit with a transistor having first and second electrodes coupled between an input and output of the rectifier circuit. A latch has an output connected to a control node of the transistor, and has first and second inputs connected to the input and output of the rectifier c |
| 6462695 |
Dynamic biasing techniques for low power pipeline analog to digital converters |
October 8, 2002 |
| A method and circuitry for implementing low-power analog-to-digital converters. More particularly, embodiments of the present invention provide an amplifier circuit for pipeline ADCs having multiple stages, some in sample mode, some in hold mode. The stages include residue amplifiers |
| 6452425 |
Automatic frequency rate switch |
September 17, 2002 |
| A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The clock's frequency is identified when its frequency falls into the set range for which the |
| 6452248 |
Low-powered, self-timed, one-time in-circuit programmable MOS fuse element and circuit |
September 17, 2002 |
| A programmable fuse structure using an MOS transistor. A voltage potential is switched across the gate of the MOS transistor, with the gate resistance causing it to heat the MOS structure. This causes a short at one or more of a number of locations in the MOS structure, thereby progr |
| 6424510 |
ESD structure for IC with over-voltage capability at pad in steady-state |
July 23, 2002 |
| The present invention provides an ESD structure that can tolerate voltages at the I/O pin, or pad, higher than the voltage allowed for such technology. More particularly, the present invention provides an electrostatic discharge integrated circuit having a first and second NMOS trans |
| 6424197 |
Rising and falling edge aperture delay control circuit in analog front end of imaging system |
July 23, 2002 |
| A programmable delay in an AFE of an imaging system which can vary both the pulse position and the pulse width. The pulse width and position are controlled by providing separate programmable delay circuits for the rising and falling edges of the desired timing signal. Combining logic |
| 6404927 |
Control point generation and data packing for variable length image compression |
June 11, 2002 |
| A simple, cost-effective compression circuit which compress raw color data without interpolation. Control points common to all the colors in a line are generated each time one of the colors exceeds the color change threshold. The change in the other color is recorded at the same time eve |
| 6359484 |
Slew-rate-control structure for high-frequency operation |
March 19, 2002 |
| The present invention provides an integrated circuit driver having multiple resistance paths that switch on at different stages of the rising and falling transitions of the driver's output signal waveform. The driver also has a control circuit configured to turn on the one or more re |
| 6351165 |
Digital jitter attenuator using an accumulated count of phase differences |
February 26, 2002 |
| A phase detector which detects the phase difference between the input clock and an output clock. That phase difference is used to gate a high frequency clock, which is provided to the clock input of an up/down counter. The phase detector also indicates whether the phase difference is |
