| Patent Number |
Title Of Patent |
Date Issued |
| 7411271 |
Complementary metal-oxide-semiconductor field effect transistor |
August 12, 2008 |
| A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second sinker, a first bu |
| 7391079 |
Metal oxide semiconductor device |
June 24, 2008 |
| A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the surface of the |
| 7338852 |
Method of forming a semiconductor device having a capacitor and a resistor |
March 4, 2008 |
| A method of simultaneously forming at least: one capacitor two resistors and one metal-oxide semiconductor. A first doped polysilicon layer/patterned interpoly oxide film/second doped polysilicon layer is formed over an exposed oxide structure. The patterned interpoly oxide forms a c |
| 7294550 |
Method of fabricating metal oxide semiconductor device |
November 13, 2007 |
| A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the surface of the |
| 7199009 |
Method for fabricating power mosfet |
April 3, 2007 |
| A method for fabricating a power MOSFET, comprising an epitaxial layer, a gate dielectric layer and a gate layer formed on a substrate, the gate dielectric layer and the gate layer defined to form a gate structure, a stacked mask and the surface of the epitaxial layer partially exposed |
| 7084033 |
Method for fabricating a trench power MOSFET |
August 1, 2006 |
| A method for fabricating a trench power MOSFET, comprising an epitaxial layer and a mask layer formed over a substrate, a trench formed in the epitaxial layer and the mask layer, a gate oxide layer formed on the trench, then the mask layer removed, a body well region formed in the ep |
| 7060567 |
Method for fabricating trench power MOSFET |
June 13, 2006 |
| A method for fabricating trench power MOSFET is described. An epitaxial layer and a mask layer having a first opening are sequentially formed on a substrate. A pair of spacers is formed on the sidewalls of the first opening. A second opening exposing the surface of the epitaxial layer is |
| 6815337 |
Method to improve borderless metal line process window for sub-micron designs |
November 9, 2004 |
| A process for reducing the risk of removing metal from an underlying metal structure during a dry etch procedure used to define a borderless, overlying metal line structure, has been developed. After formation of a damascene type, underlying metal structure, deposition of an metal layer |
| 6806136 |
Method of forming a semiconductor device having a capacitor and a resistor |
October 19, 2004 |
| The present invention relates generally to semiconductor fabrication and more specifically to simultaneous formation of capacitors, resistors and metal oxide semiconductor. |
| 6620663 |
Self-aligned copper plating/CMP process for RF lateral MOS device |
September 16, 2003 |
| A method of fabricating an RF lateral MOS device, comprising the following steps. A substrate having a gate oxide layer formed thereover is provided. A first layer of polysilicon is formed over the gate oxide layer. A second layer of material is formed over the polysilicon layer. The pol |
| 6489204 |
Save MOS device |
December 3, 2002 |
| Using current technology, the only way to further increase device density is to decrease device pitch. The present invention achieves this by introducing a sidewall doping process that effectively reduces the source width, and hence the pitch. This sidewall doping process also eliminates |
| 6255184 |
Fabrication process for a three dimensional trench emitter bipolar transistor |
July 3, 2001 |
| A process for fabricating a bipolar junction transistor, featuring an N type, polysilicon emitter structure, located in an emitter trench, and featuring a narrow width. P type base region, located directly underlying an N type, emitter region, which is formed in the semiconductor substra |
