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Elpida Memory, Inc. Patents
Assignee:
Elpida Memory, Inc.
Address:
Tokyo, JP
No. of patents:
1111
Patents:












Patent Number Title Of Patent Date Issued
RE43539 Output buffer circuit and integrated semiconductor circuit device with such output buffer circui July 24, 2012
An output buffer circuit has a main driver including a first pMOS transistor and a first nMOS transistor for driving a load, and a second pMOS transistor and a second nMOS transistor for driving the load in coaction with the first pMOS transistor and the first nMOS transistor, and a
RE40205 Semiconductor device and timing control circuit April 1, 2008
.[.Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by
RE40132 Large scale integrated circuit with sense amplifier circuits for low voltage operation March 4, 2008
Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/ou
8588023 Semiconductor memory device having selective activation circuit for selectively activating circu November 19, 2013
A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation ci
8588019 Semiconductor device having current change memory cell November 19, 2013
A semiconductor device comprises a first transistor connected between a bit line and a sense node, and a second transistor amplifying a signal of the sense node. A first potential applied to a gate of the first transistor, a second potential supplied to the sense node, and a third po
8588011 Semiconductor device and method November 19, 2013
A semiconductor device is provided with first and second main word lines, and a control circuit. The control circuit, in response to a command signal received from outside of the semiconductor device, activates the first main word line at a first timing, and activates the second main
8587117 Stacked semiconductor chips having circuit element provided with each of the semiconductor chips November 19, 2013
A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor c
8587097 Semiconductor device that suppresses malfunctions due to noise generated in internal circuit November 19, 2013
A semiconductor device includes a first pad row and a second pad row, a first ground potential supply electrode which is connected to a first interconnect provided near the first pad row, and a second ground potential supply electrode which is connected to a second interconnect provi
8587035 Device November 19, 2013
A device includes a semiconductor substrate, a first local bit line formed in the semiconductor substrate and elongated in a first direction, a first insulating layer on the semiconductor substrate, a first global bit line formed on the first insulating layer, a first path formed in the
8586430 Method of forming dielectric film and capacitor manufacturing method using the same November 19, 2013
In a method of manufacturing a capacitor, a lower electrode of a capacitor is formed on or above a semiconductor substrate. An ozone gas and an inert gas are simultaneously introduced for a predetermined period into a reaction chamber of an atomic layer deposition apparatus in which
8584061 Semiconductor device November 12, 2013
To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an out
8582337 Semiconductor memory device, method of controlling read preamble signal thereof, and data transm November 12, 2013
A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second
8581758 Semiconductor device, method for controlling the same, and data processing system including semi November 12, 2013
A semiconductor device includes a multiplexer and an output buffer. The multiplexer includes: n switches (n is an integer of 2 or greater) each including an input node receiving a different data signal and an output node coupled to an input node of the output buffer; and a plurality of
8581649 Semiconductor device and information processing system November 12, 2013
The semiconductor device includes an output driver and a characteristic switching circuit that switches characteristics of the output driver. The characteristic switching circuit mutually matches a rising time and a falling time of an output signal output from the output driver, when a
8581417 Semiconductor device stack with bonding layer and wire retaining member November 12, 2013
In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the pluralit
8581315 Semiconductor device having cylindrical lower electrode of capacitor and manufacturing method th November 12, 2013
To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting fi
8580681 Manufacturing method of device November 12, 2013
A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner
8580649 Method for manufacturing semiconductor device November 12, 2013
Disclosed is a method for manufacturing a semiconductor device, which provides an isolation region in which a dense silicon oxide film is formed in a trench that requires high aspect ratio. The method includes forming an isolation trench using, as an etching mask, a nitride mask film
8576656 Latency counter, semiconductor memory device including the same, and data processing system November 5, 2013
A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output sele
8576652 Semiconductor memory device, memory system including memory controller, and refresh control meth November 5, 2013
A semiconductor memory device has an operation mode in which a read/write operation is performed in response to a command supplied externally in synchronization with a clock, and a power-down mode in which no external read/write command is accepted. The semiconductor memory device perfor
8576647 Semiconductor device November 5, 2013
A semiconductor device includes a bit line; a data bus line corresponding to the bit line; a selection transistor that controls electrical connection between the bit line and the data bus line; a write amplifier that writes data to the bit line through the data bus; and a test circui
8576639 Memory device having switch providing voltage to bit line November 5, 2013
A memory device in which a circuit reads a cell condition. A terminal provides voltage to a bit line of the circuit via a switch. The circuit outputs and enables storage of a first logical value when the voltage provided from the terminal does not exceed a threshold value. The circuit
8576610 Semiconductor device having floating body type transistor November 5, 2013
A semiconductor device is disclosed in which a signal line and a drive circuit driving the signal line in response to a signal to be transmitted are provided. A transistor of a floating body type is further provided that includes a gate, a source, a drain, and a body between the source
8575763 Semiconductor device and method of manufacturing the same November 5, 2013
A semiconductor device includes a first wiring hoard, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is di
8574998 Leakage reduction in DRAM MIM capacitors November 5, 2013
A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (<30
8574997 Method of using a catalytic layer to enhance formation of a capacitor stack November 5, 2013
A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing
8574996 Method of manufacturing semiconductor device November 5, 2013
A method of manufacturing a semiconductor device comprises: forming a processing target; forming a first supporter on the processing target; forming a first mask so as to contact one side surface of the first mask with a side surface of the first supporter; patterning the processing
8574985 Methods for depositing high-K dielectrics November 5, 2013
Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact an
8574983 Method for fabricating a DRAM capacitor having increased thermal and chemical stability November 5, 2013
A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode
8570815 Semiconductor device and method of controlling the same October 29, 2013
When overdriving a first power supply voltage supplied to a sense amplifier, a line for the first power supply voltage and a line for a second power supply voltage which is higher than the first power supply voltage are connected to each other by a first transistor, thereby boosting
8569898 Semiconductor device October 29, 2013
Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that includes a slot, a large number of external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers
8569835 Semiconductor device October 29, 2013
A semiconductor device includes a first pad, and a sub-trunk line elongated in a first direction; a main-trunk line arranged between the first pad and the sub-trunk line and elongated in the first direction. The semiconductor device further includes a first plug line elongated in a s
8569830 Semiconductor device having vertical MOS transistor and method for manufacturing the semiconduct October 29, 2013
In a vertical MOS transistor in which a semiconductor pillar is formed by etching a semiconductor substrate in a portion surrounded by an isolation film, the semiconductor pillar is covered with a gate insulating film and a gate electrode to be made a channel part, and diffusion layers t
8569819 Doped electrodes for DRAM applications October 29, 2013
A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or
8565036 Semiconductor memory device including pull-down transistors for non-selected word lines October 22, 2013
A semiconductor memory device includes a plurality of word lines wired in a first direction, a plurality of bit lines wired in a direction crossing the first direction, a memory cell array including a plurality of DRAM cells provided corresponding to intersections between the word lines
8565032 Semiconductor device October 22, 2013
A semiconductor device includes: a clock generator generating a first internal clock signal based on an external clock signal; a clock divider generating second and third internal clock signals based on the first internal clock signal and including an edge adjustor adjusting a timing
8564361 Semiconductor device and method of controlling the same October 22, 2013
A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V.sub.2 from a first voltage V.sub.1; and a control circuit that generates the current control signal OVDR, makes a current that is flowed b
8564037 Semiconductor device having isolation groove and device formation portion October 22, 2013
A semiconductor device may include, but is not limited to, a semiconductor substrate having a device isolation groove defining first to fourth device formation portions. The second device formation portion is separated from the first device formation portion. The third device formati
8563392 Method of forming an ALD material October 22, 2013
In some embodiments of the present invention, methods are developed wherein a gas flow of an electron donating compound (EDC) is introduced in sequence with a precursor pulse and alters the deposition of the precursor material. In some embodiments, the EDC pulse is introduced sequent
8300487 Semiconductor device October 30, 2012
A semiconductor device comprises a plurality of terminals, a plurality of drive units corresponding to the plurality of terminals, and a data control unit. The data control unit outputs parallel data applied to the plurality of terminals to the plurality of drive unit in a normal ope
8300484 Semiconductor device and semiconductor memory device October 30, 2012
A semiconductor device comprises a memory cell array including memory cells, a first bit line transmitting data stored in a selected memory cells, a single-ended first sense amplifier amplifying a signal voltage of the first bit line and converting the voltage into an output current,
8300480 Semiconductor device having sense amplifiers supplied with an over-drive voltage in a normal mod October 30, 2012
A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than
8299847 Semiconductor device and data processing system including the same October 30, 2012
A pair of power nodes of a logic circuit that needs to output a high level at the time of standby is connected to third and fifth dummy power lines and a pair of power nodes of a logic circuit that needs to output a low level at the time of standby are connected to second and sixth dummy
8299845 Semiconductor device October 30, 2012
A semiconductor device includes a first circuit, a second circuit, and a first voltage dividing circuit. The first circuit is coupled to a first terminal. The first circuit is operable by a first voltage supplied from the first terminal. The second circuit is coupled through a first
8299829 Clock generation circuit, semiconductor device including the same, and method of generating cloc October 30, 2012
To provide a DLL circuit incorporating a duty adjustment circuit that is independent of the frequency of a clock signal. The DLL circuit includes: a delay line that delays a first internal clock signal to generate a second internal clock signal; a counter circuit that specifies an amount
8298941 Method of manufacturing semiconductor device October 30, 2012
A method of manufacturing a semiconductor device includes, but is not limited to, the following processes. A seed layer is formed over a substrate. The seed layer includes first, second, and third portions. A first electrode covering the first portion of the seed layer is formed with
8298940 Semiconductor memory device and manufacturing method thereof October 30, 2012
A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the f
8295119 Latency counter, semiconductor memory device including the same, and data processing system October 23, 2012
A latency counter includes a counter circuit and a point-shift FIFO circuit. Latch circuits included in the point-shift FIFO circuit are divided into n groups having wired-OR outputs, and an output of a latch circuit that belongs to a group different from a current group is selected
8295113 Semiconductor device October 23, 2012
Disclosed is a semiconductor device including: a first switch controlling connection between a first data line pair a second data line pair; a first amplifier connected to the first data line pair; a second switch controlling the connection between the second data line pair and a third
8295101 Semiconductor device October 23, 2012
A semiconductor device includes a sense amplifier, transistors selectively establishing electrical connection between the sense amplifier and a data bus, depending on address; a write amplifier connected to the data bus, an external terminal outputting data from a memory cell to outs

 
 
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