| Patent Number |
Title Of Patent |
Date Issued |
| RE40205 |
Semiconductor device and timing control circuit |
April 1, 2008 |
| .[.Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by |
| RE40132 |
Large scale integrated circuit with sense amplifier circuits for low voltage operation |
March 4, 2008 |
| Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/ou |
| 7630275 |
Latency counter |
December 8, 2009 |
| A latency counter includes: a point-shift type FIFO circuit having plural latch circuits connected in parallel, each latch circuit including an input gate and an output gate, and having an internal command MDRDT supplied in common to the input gates; and a selector that makes any one |
| 7629810 |
Input and output circuit |
December 8, 2009 |
| Stable testing is performed on an input and output circuit. An output stage outputting output signal to input/output terminal DQ comprises: a differential pair formed from an Nch transistor N1, having as load a Pch transistor P1 and resistance element R1, and an Nch transistor N2, having |
| 7627442 |
Semiconductor device having a test-voltage generation circuit |
December 1, 2009 |
| A semiconductor device includes an internal power supply line, a first power supply circuit, and second power supply circuits. The first power supply circuit includes an ordinary-voltage generation circuit supplying an ordinary voltage to the internal power supply line during an ordinary |
| 7626862 |
Semiconductor memory device |
December 1, 2009 |
| A semiconductor memory device comprises a memory cell array having a hierarchical word line structure including main word lines and sub-word lines; a main word driver for driving a non-selected main word line to high and for driving and activating a selected main word line to low; and |
| 7623402 |
Semiconductor memory device operating a self refreshing and an auto refreshing |
November 24, 2009 |
| An oscillating period of an oscillator is configured to be adjustable by CODEi output from a ROM circuit, and a circuit is configured so that the oscillating period is equal to a period p times a tRAS period during self refreshing. An n-bit counter counts up based on the output of the |
| 7623398 |
Semiconductor memory device and semiconductor device |
November 24, 2009 |
| Disclosed is a module where semiconductor memory devices each having a DLL (Delay Lock Loop) are stacked or a multi-chip module (MCM) having the semiconductor memory devices, a dedicated pad for sharing a clock signal between one of the semiconductor memory devices and other semiconducto |
| 7622960 |
Metastable-resistant phase comparing circuit |
November 24, 2009 |
| A phase comparing circuit includes a first storage circuit for reading an external clock signal based on a control clock signal; first and second inverters for inverting a signal from the first storage circuit based respectively on first and second threshold levels; third and fourth |
| 7622350 |
Method of manufacturing semiconductor device having cell transistor with recess channel structur |
November 24, 2009 |
| A method of manufacturing a semiconductor device is provided. Device separation portions defining first, second and third regions are formed in a substrate. A recess is formed at the first region. An N-type well is formed at the third region. An N-type polysilicon layer is formed at the |
| 7620837 |
Data transmission system and data transmission apparatus |
November 17, 2009 |
| A data transmission system including a slave device (30) and a master device (10) is disclosed. Slave device (30) may include a slave side clock signal generator section (32) for generating a slave side clock signal (CLKSOUT), a phase adjusting circuit (40) for controlling a phase of |
| 7619911 |
Semiconductor integrated circuit device |
November 17, 2009 |
| In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP |
| 7618869 |
Manufacturing method for increasing product yield of memory devices suffering from source/drain |
November 17, 2009 |
| A DRAM device includes contact pads having a bottom in contact with a corresponding source/drain region 21 and a top in contact with a bottom of an overlying contact plug. The source/drain region has a recess caused by misalignment of the contact pad with respect to the source/drain |
| 7618847 |
Bonding method of semiconductor and laminated structure fabricated thereby |
November 17, 2009 |
| A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at |
| 7615870 |
Semiconductor device, manufacturing method thereof, and connection method of circuit board |
November 10, 2009 |
| Cut pieces of a flexible tape respectively having positioning holes are superposed on a substrate having positioning holes, while positioning the substrate and the cut pieces by inserting a positioning pin into the positioning holes respectively, so that one side of the substrate faces |
| 7615460 |
Hard mask technique in forming a plug |
November 10, 2009 |
| A method for manufacturing a semiconductor device includes the steps of forming a conductive hard mask coupled to the semiconductor substrate via discharge plugs on a thick insulating film, selectively etching the thick insulating film by using the conductive hard mask to form cylindrica |
| 7613056 |
Semiconductor memory device |
November 3, 2009 |
| In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired.The semiconductor memory device has a plurality of memory blocks, and the memory b |
| 7613038 |
Semiconductor integrated circuit device |
November 3, 2009 |
| There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column |
| 7612579 |
Output circuit of semiconductor device and semiconductor device including thereof |
November 3, 2009 |
| An output circuit includes a counter circuit that generates an ODT control signal ODTa, plural driver circuits having the ODT function, a synchronizing circuit that synchronizes a signal transmitted from the counter circuit to the driver circuit with an internal clock DLL, a first se |
| 7611947 |
Method of manufacturing semiconductor device |
November 3, 2009 |
| A method of manufacturing a semiconductor device of the present invention consists of forming a trench in a trench-type cell transistor region; forming a gate insulating film and a gate material layer on a semiconductor substrate; forming a photoresist layer on the semiconductor subs |
| 7609572 |
Semiconductor memory device |
October 27, 2009 |
| In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during se |
| 7606094 |
Semiconductor memory device and control method thereof |
October 20, 2009 |
| A semiconductor memory device of the invention has memory cells arranged at intersections of bit lines and word lines, and comprises a sense amplifier for amplifying a minute potential difference appearing on a bit line pair; a power supply line pair including first and second power |
| 7603592 |
Semiconductor device having a sense amplifier array with adjacent ECC |
October 13, 2009 |
| A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array |
| 7598549 |
Semiconductor device having a silicon layer in a gate electrode |
October 6, 2009 |
| A CMOS device includes a silicon substrate, a gate insulating film, and a gate electrode including a silicon layer doped with boron and phosphorous, a tungsten nitride layer and a tungsten layer. A ratio of a maximum boron concentration to a minimum boron concentration in a boron con |
| 7596051 |
Semiconductor memory integrated circuit |
September 29, 2009 |
| A semiconductor memory integrated circuit having an X-row controller which includes a high-speed-operation control circuit by which when receiving a bank active signal, a period for stopping a latch circuit from receiving the X address is produced after a predetermined time has elapsed, |
| 7595645 |
Calibration circuit and semiconductor device incorporating the same |
September 29, 2009 |
| Impedance adjusting transistors are once inactivated on every occasion of changing an impedance adjusting code. After restoring the potential to an initially set potential by once inactivating the impedance adjusting transistors, the state of the transistors is switched according to the |
| 7595236 |
Method for production of semiconductor device having a hole extending through a first insulating |
September 29, 2009 |
| A short circuit with an adjacent hole is prevented. By enlarging a hole diameter in the lower part of the hole, a stable storage node is formed without causing a decrease in capacitance. Provided is a method for production of a semiconductor device, comprising the steps of: forming t |
| 7592267 |
Method for manufacturing semiconductor silicon substrate and apparatus for manufacturing the sam |
September 22, 2009 |
| This invention provides a method for manufacturing a semiconductor silicon substrate by use of carbon dioxide in a supercritical state, which method is capable of making the semiconductor silicon substrate highly reliable one. Specifically, this invention provides a method for manufactur |
| 7592249 |
Method for manufacturing a semiconductor device |
September 22, 2009 |
| A highly reliable method for forming contact plugs is provided. The method can prevent short circuiting from occurring between self aligned contact plugs and word lines or between self aligned contact plugs and bit lines by applying a material, whose etching speed ratio relative to that |
| 7592234 |
Method for forming a nitrogen-containing gate insulating film |
September 22, 2009 |
| A method for forming a nitrogen-containing gate insulating film includes the steps of forming a silicon oxide film on a silicon substrate, nitriding the top portion of the silicon oxide film to form a thin silicon nitride layer, and forming a silicon nitride film on the silicon nitri |
| 7590012 |
Semiconductor storage device |
September 15, 2009 |
| Semiconductor storage device of reduced layout area having memory cell rows accessed selectively. Memory cells, each including a programmable resistive element, are connected by a bit line to form a memory cell row. Selecting circuit for selecting a memory cell row includes a first NMOS |
| 7589364 |
Electrically rewritable non-volatile memory element and method of manufacturing the same |
September 15, 2009 |
| A non-volatile memory element includes a first interlayer insulation layer 11 having a first through-hole 11a, a second interlayer insulation layer 12 having a second through-hole 12a formed on the first interlayer insulation layer 11, a bottom electrode 13 provided in the first thro |
| 7589344 |
Semiconductor device and method of producing the same |
September 15, 2009 |
| In a semiconductor device, a phase change layer is formed as a side wall and is therefore reduced in volume. Even if the number of times of rewriting is small, the phase change layer is entirely used as a phase change region. Therefore, the phase change region is not increased in vol |
| 7589024 |
Process for producing semiconductor integrated circuit device |
September 15, 2009 |
| Recently, with shortened wavelengths employed in aligners, it is now difficult to use a material containing a benzene ring as a photoresist material. Since resist has extremely low plasma resistance, formation of deep holes using a photoresist as a dry etching mask is difficult. Under |
| 7586807 |
Semiconductor memory device |
September 8, 2009 |
| A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at |
| 7585736 |
Method of manufacturing semiconductor device with regard to film thickness of gate oxide film |
September 8, 2009 |
| A method of manufacturing a semiconductor device includes steps (a) to (d). The step (a) is a step of forming a first insulating film and a nitride film on a semiconductor substrate in this order. The step (b) is a step of removing said first insulating film and said nitride film in a |
| 7583550 |
Semiconductor memory device |
September 1, 2009 |
| In a sense amplifier circuit having a plurality of sense amplifier portions arranged in order, each of the sense amplifier portions includes a transistor that supplies a bit line potential to a bit line pair in a corresponding column of a memory cell array and a gate electrode for su |
| 7582889 |
Electrically rewritable non-volatile memory element and method of manufacturing the same |
September 1, 2009 |
| A non-volatile memory element includes a lower electrode, an upper electrode, a recording layer arranged between the lower electrode and the upper electrode and containing a phase change material, and a bit line directly arranged on the upper electrode. The bit line is formed to be o |
| 7582554 |
Method for manufacturing semiconductor device |
September 1, 2009 |
| A method for manufacturing a semiconductor device according to the present invention includes the steps of providing a semiconductor substrate in which an element isolation region and active regions surrounded by the element isolation region are formed, forming a plurality of conductive |
| 7580321 |
Synchronous semiconductor memory device |
August 25, 2009 |
| A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of |
| 7580307 |
Semiconductor memory device |
August 25, 2009 |
| An apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the contents of the storage units to each other as to whether or not the counter outputs co |
| 7580277 |
Memory device including a programmable resistance element |
August 25, 2009 |
| Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with |
| 7577045 |
Semiconductor memory device |
August 18, 2009 |
| A semiconductor memory device includes transistors that supply a higher write potential and a lower write potential to a sense amplifier, respectively, an overdrive transistor that supplies an overdrive potential to the sense amplifier, and a control circuit that changes a gate-sourc |
| 7576579 |
DLL circuit and semiconductor device including the same |
August 18, 2009 |
| A DLL circuit includes a first delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK1, a second delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK2, a synthesizing circuit that synthesizes outputs of these delay |
| 7576566 |
Level-conversion circuit |
August 18, 2009 |
| An independent control signal is transmitted to each of a driver control unit and an output transistor, so as to prevent the driver control unit and the output transistor from being made to operate at the same time and reduce through-current flows. Since the transistor ratio can be selec |
| 7576433 |
Semiconductor memory device and manufacturing method thereof |
August 18, 2009 |
| A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the f |
| 7576421 |
Semiconductor device having a multi-layered semiconductor substrate |
August 18, 2009 |
| A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to th |
| 7576389 |
Semiconductor device and manufacture method thereof |
August 18, 2009 |
| The present invention provides a trench gate Tr having a first gate electrode and a second gate electrode in the inside of a groove. The first gate electrode is provided in a groove lower part defining a channel of the Tr with a gate oxide film interposed between the first gate elect |
| 7576016 |
Process for manufacturing semiconductor device |
August 18, 2009 |
| An objective of this invention is to solve the problem that in ALD film deposition using a vertical batch processing machine advantageous for improving a throughput, reliability in a dielectric body formed on the bottom of a hole such as a capacitor formed on a semiconductor substrate |
| 7573778 |
Semiconductor memory device |
August 11, 2009 |
| A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address |
