| Patent Number |
Title Of Patent |
Date Issued |
| 7361571 |
Method for fabricating a trench isolation with spacers |
April 22, 2008 |
| A method for forming a shallow trench isolation (STI) in a semiconductor device, is presented. In one embodiment, the method includes successively forming a pad oxide and a pad nitride on a silicon substrate, successively etching the pad nitride, the pad oxide, and the silicon substr |
| 7262072 |
CMOS image sensor and method for fabricating the same |
August 28, 2007 |
| A CMOS image sensor and a method for fabricating the same are disclosed, in which double microlenses are formed using materials having different refractive indexes to improve concentration efficiency of light, thereby improving the characteristics of the image sensor. |
| 7211847 |
CMOS image sensor |
May 1, 2007 |
| A CMOS image sensor includes a photo sensing device for generating photo charges, a floating diffusion region for storing the photo charges generated by the photo sensing device therein, a transfer transistor connected between the photo sensing device and the floating diffusion regio |
| 7141880 |
Metal line stacking structure in semiconductor device and formation method thereof |
November 28, 2006 |
| The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performin |
| 7132364 |
Method for forming metal interconnect of semiconductor device |
November 7, 2006 |
| A method for forming a metal interconnect of a semiconductor device defined by a fine trench or via is disclosed. The method includes forming a first interconnect insulating layer on a substrate. A via hole is formed on a predetermined portion of the first interconnect insulating lay |
| 7112473 |
Double side stack packaging method |
September 26, 2006 |
| In a double side stack packaging a plurality of chips, a hole is formed in a substrate. A first chip is attached to a bottom surface of the substrate by using a thermo compression and is electrically interconnected to terminals formed at sidewall of the hole using a wire bonding. Nex |
| 7109543 |
Semiconductor device having trench capacitor and method for fabricating the same |
September 19, 2006 |
| A semiconductor device and a method for fabricating the same. The device comprises a silicon substrate having a conductive well; a trench formed in the conductive well; a plate electrode formed on the sidewall of the trench; a capacitor insulating film and a storage node electrode; a fir |
| 7094643 |
Method of forming gate of flash memory cell |
August 22, 2006 |
| A method of forming a gate of a flash memory cell, by which a coupling effect between floating and control gates can be enhanced by forming a polysilicon spacer in forming the floating gate to increase a surface area of the floating gate. The gate is formed by forming a nitride layer |
| 7080332 |
SPICE simulation system for diode and method of simulation using the same |
July 18, 2006 |
| A system and method for simulating a diode device measures electrical characteristics of a plurality of diodes; normalizes the measured electrical characteristics of the diode; extracts a plurality of device parameters of each of the diodes from the normalized characteristics; conver |
| 7074682 |
Method for fabricating a semiconductor device having self aligned source (SAS) crossing trench |
July 11, 2006 |
| In order to provide a method for preventing the channel length from being shortened as well as reducing the SAS resistance, the semiconductor device according to the present invention is manufactured by forming continuous linear trench lines on a semiconductor substrate, forming gate |
| 7071501 |
Image sensor having integrated single large scale pixel and pixel separation pattern |
July 4, 2006 |
| An image sensor is disclosed where individual photo diodes of the respective unit cells separated by an element isolating layer are physically integrated into a single large scale pixel formed widely on a semiconductor substrate so as to hold the pixels in common. A pixel separation |
| 7067431 |
Method of forming damascene pattern in a semiconductor device |
June 27, 2006 |
| The present invention relates to a method of forming damascene pattern in a semiconductor device, and the method includes forming an insulating layer on a bottom wiring, forming via holes exposing a part of the bottom wiring by removing the insulating layer selectively, filling insides o |
| 7067360 |
Method of fabricating a fin field effect transistor |
June 27, 2006 |
| A method of fabricating a fin field effect transistor is disclosed. An example method forms a thermal oxide layer as a hard mask for etching a silicon fin on an SOI substrate, transcribes a fin pattern, forms a fin FET body by etching using the fin pattern as an etch mask, and restores a |
| 7064383 |
Non-volatile memory device |
June 20, 2006 |
| A non-volatile memory including a semiconductor substrate, and a SONOS electrode on the semiconductor substrate, where the SONOS electrode has a channel area defined underneath. The memory also includes a first layer in contact with a side of the SONOS electrode, a second layer in contac |
| 7064381 |
Non-volatile memory device having upper and lower trenches and method for fabricating the same |
June 20, 2006 |
| Non-volatile memory device, and method for fabricating the same are disclosed. By forming floating gate trenches in memory regions and filling the trenches with floating gate material, a step height of a with the floating gate/ONO/control gate structure is reduced to the level of a g |
| 7064369 |
Method for manufacturing a semiconductor device including a PIP capacitor and a MOS transistor |
June 20, 2006 |
| In a method for fabricating a semiconductor device including a PIP capacitor and a MOS transistor, an isolator film is formed on a semiconductor substrate and then etched to expose an active region of the substrate. An epitaxial film is then formed by performing a selective epitaxial |
| 7061045 |
Flash memory cell and method for manufacturing the same |
June 13, 2006 |
| The present invention relates to a flash memory and a method for manufacturing the same, capable of minimizing resistance of the common source line in the flash memory cell manufacturing process. In the memory cell manufacturing method according to the embodiment of the present inven |
| 7060609 |
Method of manufacturing a semiconductor device |
June 13, 2006 |
| A method of manufacturing a semiconductor device is disclosed wherein a tungsten single atomic layer is deposited in a contact or via hole of a silicon substrate. A tungsten nitride (WN) layer is formed by plasma processing the tungsten single atomic layer using an atomic layer depos |
| 7060603 |
Methods of forming metal wiring of semiconductor devices including sintering the wiring layers a |
June 13, 2006 |
| A formation method of metal wiring of a semiconductor device is disclosed. According to one example, an example method may include forming a metal wire on a pre metal dielectric ("PMD") on a semiconductor substrate; patterning and sintering the metal wire; forming an insulating layer on |
| 7056814 |
Methods of manufacturing a MOS transistor |
June 6, 2006 |
| Methods of manufacturing MOS transistors which are capable of suppressing a short channel effect are disclosed. The short channel effect is suppressed by forming source/drain regions of a shallow junction and sufficiently doping a gate. An illustrated method includes: forming a gate |
| 7056647 |
Flash memory with reduced source resistance and fabrication method thereof |
June 6, 2006 |
| A flash memory device having a reduced source resistance and a fabrication method thereof are disclosed. An example flash memory includes a cell region including a gate, a source line, a drain contact, and a cell trench area for device isolation on a silicon substrate. The example fl |
| 7051454 |
Method for etching a metal layer in a semiconductor device |
May 30, 2006 |
| A method for etching a metal layer on which an oxide-based ARC layer is coated in a semiconductor device comprises the step of performing a dry cleaning process by using a Cl.sub.2/CHF.sub.3 based gas, after dry cleaning the ARC layer by using the oxide-based gas. As a result, the et |
| 7049239 |
STI structure and fabricating methods thereof |
May 23, 2006 |
| An STI structure and fabricating method thereof are disclosed. The STI fabricating method comprises forming a pad oxide layer and a first nitride layer on a substrate. A trench is formed by etching the first nitride layer, the pad oxide layer and the substrate. An oxide and a second |
| 7049195 |
Methods of fabricating non-volatile memory devices |
May 23, 2006 |
| The present disclosure is directed to a non-volatile memory device having a SONOS structure and a method of fabricating the same, wherein the non-volatile memory device having the SONOS structure is fabricated using a simple and lower cost method by greatly reducing the number of the |
| 7042062 |
Device isolation structures of semiconductor devices and manufacturing methods thereof |
May 9, 2006 |
| A device isolation structure of a semiconductor device may be a silicon wafer, a trench formed in the silicon wafer to have a predetermined depth, a first thermal oxide layer formed to an inner surface of the trench, a pad oxide layer formed on the silicon wafer, a second thermal oxi |
| 7041597 |
Semiconductor device having void free contact and method for fabricating the contact |
May 9, 2006 |
| The present invention relates to a semiconductor device and a method for fabricating a contact of the semiconductor device, and in particular, to the method for fabricating a semiconductor contact of the device for electrically coupling upper and lower metal wires or coupling an elec |
| 7037858 |
Method for manufacturing semiconductor device including an ozone process |
May 2, 2006 |
| A method for manufacturing a semiconductor device includes forming a barrier layer on an individual device formed on a semiconductor substrate and including a MOS transistor. An ozone process is performed on the barrier layer. A pre-metal dielectric (I'MD) layer is then formed on the |
| 7037836 |
Method of manufacturing a semiconductor device without oxidized copper layer |
May 2, 2006 |
| A semiconductor device which effectively reduces copper oxide layers on copper conductive lines is disclosed. The method includes forming a first insulating layer on a semiconductor substrate; forming a first conductive line by depositing a conductive material on the first insulating lay |
| 7033932 |
Method for fabricating a semiconductor device having salicide |
April 25, 2006 |
| The present invention can protect from degradation of product reliability of a semiconductor caused during formation of a salicide suppression layer. In order to achieve this, unlike the conventional method in which the sidewall spacer of the gate electrode and the salicide suppression |
| 7033875 |
MOS transistor and fabrication method thereof |
April 25, 2006 |
| A MOS transistor and a method for fabricating the MOS transistor. The present invention enables implementation of a stable semiconductor device that is capable of protecting against leakage current generation by improving the "LDD effect" and securing a large process margin by adjust |
| 7030454 |
Semiconductor devices and methods of forming a trench in a semiconductor device |
April 18, 2006 |
| Semiconductor devices and methods to form a trench in a semiconductor device are disclosed. A disclosed process comprises: forming a hollow by etching a portion of a semiconductor substrate; forming a side wall layer in an inner side wall of the hollow; forming a trench by further etchin |
| 7030021 |
Method of fabricating metal interconnection of semiconductor device |
April 18, 2006 |
| A method of fabricating a metal interconnection of semiconductor device is disclosed. A metal interconnection fabricating method according to the present invention comprises the steps of depositing a metal layer on a substrate having a predetermined structure; patterning a bottom metal |
| 7030005 |
Method of manufacturing semiconductor device |
April 18, 2006 |
| Method for forming intermetal dielectric layer is disclosed including steps of: preparing a substrate with wiring on a lower insulating layer, the wiring having a plurality of separating portions; forming first and second water marks on the lower insulating layer located in the separ |
| 7029998 |
Formation method of gate electrode in a semiconductor process |
April 18, 2006 |
| The present invention is directed to a method of forming a gate electrode in a semiconductor device, which is capable of reducing a line width of the gate electrode by performing a photolithography process after defining a wide region on which a gate electrode is located on a photore |
| 7029979 |
Methods for manufacturing semiconductor devices |
April 18, 2006 |
| Methods for manufacturing semiconductor devices are disclosed. In a disclosed method, a first nitride layer and a device isolation oxide layer are etched to thereby expose a portion of a silicon substrate where an active region is to be formed. An epitaxial growth is performed on the |
| 7026203 |
Method for forming dual gate electrodes using damascene gate process |
April 11, 2006 |
| A method for forming dual gate electrodes using a damascene gate process is disclosed. A disclosed method comprises: growing a first gate oxide layer on a semiconductor substrate; performing a thermal treatment for a first gate oxide layer; removing a predetermined part of the first gate |
| 7022601 |
Method of manufacturing a semiconductor device |
April 4, 2006 |
| A method of manufacturing a semiconductor device is disclosed wherein a WSiN layer is deposited in a contact hole as a barrier metal using an ALD process. A tungsten layer is deposited on the WSiN layer in the nucleation stage thereof. Then, using a CVD process, the contact hole is c |
| 7022576 |
Method of manufacturing a semiconductor device |
April 4, 2006 |
| The present invention relates to a method of manufacturing a semiconductor device. According to the present invention, a sidewall layer containing impurities is formed on a part of gate electrode, thereby forming a low concentration source/drain electrode for a lightly doped drain (LDD) |
| 7020007 |
Non-volatile static random access memory |
March 28, 2006 |
| Non-volatile SRAMs having an improved recall characteristic are disclosed. An illustrated non-volatile SRAM includes a plurality of unit memory cells arranged in an array. Each of the plurality of unit memory cells comprises a SRAM unit and a non-volatile circuit. The non-volatile ci |
| 7018907 |
Methods for forming shallow trench isolation structures |
March 28, 2006 |
| Methods for forming shallow trench isolation structures are disclosed. In a disclosed example, after a trench is formed in a substrate, an oxide layer is formed on sidewalls and a bottom of the trench. Then, a metal or poly-silicon layer is formed on the oxide layer. Next, a portion of t |
| 7018899 |
Methods of fabricating lateral double-diffused metal oxide semiconductor devices |
March 28, 2006 |
| Methods for fabricating LDMOS transistors are disclosed. A disclosed method includes: forming a device isolation structure in a semiconductor substrate through an STI process; forming a photoresist pattern exposing the device isolation structure; forming double diffused wells by impl |
| 7015114 |
Trench in semiconductor device and formation method thereof |
March 21, 2006 |
| A method of forming a trench in a semiconductor device includes forming a sacrificial layer on a silicon wafer and selectively etching the sacrificial layer to form a LOCOS opening having a predetermined width. Thermal oxidation is performed on a portion of the silicon wafer exposed |
| 7015103 |
Method for fabricating vertical transistor |
March 21, 2006 |
| A method for fabricating a vertical transistor including forming a first junction area in a semiconductor substrate, forming a polysilicon layer by using an epitaxial growth in the substrate, forming a second junction area in the polysilicon layer, and forming a plug junction area in the |
| 7009301 |
Semiconductor package with a heat spreader |
March 7, 2006 |
| A semiconductor package capable of spreading heat includes an upper PCB and a lower PCB connected to a first chip and a second chip by using gold bumps, respectively. Also the semiconductor package includes a heat spreader and thermally conductive members. The heat spreader spreads the |
| 7005383 |
Apparatus and methods of chemical mechanical polishing |
February 28, 2006 |
| Disclosed are apparatus and methods of chemical mechanical polishing a semiconductor wafer to minimize formation of scratches on a surface of a wafer. According to one example, a method of planarizing a pattern of a wafer by rotating the wafer that is fixed to a carrier head, on a po |
| 7005348 |
Methods for fabricating semiconductor devices |
February 28, 2006 |
| Methods for fabricating semiconductor devices are disclosed. An illustrated method includes: etching a semiconductor substrate to form a trench, forming an ONO film on the semiconductor substrate, removing the ONO film from the upper surface of the semiconductor substrate while leavi |
| 7001843 |
Methods of forming metal lines in semiconductor devices |
February 21, 2006 |
| Methods for forming metal lines in semiconductor devices are disclosed. One example method may include forming a lower adhesive layer on a semiconductor substrate; forming a metal layer including aluminum on the lower adhesive layer; forming an anti-reflection layer on the metal laye |
| 7001842 |
Methods of fabricating semiconductor devices having salicide |
February 21, 2006 |
| Methods for fabricating a semiconductor device with salicide are disclosed. One example method includes forming a gate electrode structure having a gate oxide film, a gate electrode, and a protection film stacked on a substrate in succession, and gate spacers on sidewalls of the stack |
| 7001815 |
Method of manufacturing semiconductor device with triple gate insulating layers |
February 21, 2006 |
| An object of the present invention is to provide a method of manufacturing a semiconductor device with triple gate insulating layers that is capable of easily obtaining thicknesses and good qualities of the gate insulating layers being opportune to multiple devices.In the present inventi |
| 6998324 |
Methods of fabricating silicon on insulator substrates for use in semiconductor devices |
February 14, 2006 |
| Example methods of fabricating a silicon on insulator substrate are disclosed. One example method may include forming a plurality of trenches on a substrate, forming an insulation layer on the trenches, removing a portion of the insulation layer formed on the trenches to partially ex |
