| Patent Number |
Title Of Patent |
Date Issued |
| 5845133 |
Virtualized functions within a microprocessor |
December 1, 1998 |
| A system and method for virtualizing external pins and their internal functions within a microprocessor employing an operating system independent interrupt and N subhandlers to virtual the equivalent functions of the pins ordinarily performed by extrinsic circuitry internal to the mi |
| 5838897 |
Debugging a processor using data output during idle bus cycles |
November 17, 1998 |
| A processor for outputting processor state information during idle bus cycles to facilitate the diagnosing and debugging of a processor. The processor includes a plurality of external pins for communicating data from the processor; a visibility register for selecting one of a plurality |
| 5835967 |
Adjusting prefetch size based on source of prefetch address |
November 10, 1998 |
| A prefetch unit is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. Normally, the prefetch unit performs split prefetching by generating low and high prefetch addresses in a single clock, with the |
| 5805879 |
In a pipelined processor, setting a segment access indicator during execution stage using except |
September 8, 1998 |
| In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages, the processor capable of addressing segments of system memory coupled thereto, a circu |
| 5784713 |
Address calculation logic including limit checking using carry out to flag limit violation |
July 21, 1998 |
| Address calculation logic in which an adder carry out flags a segment limit violation is used, in an exemplary embodiment, in a 486 type microprocessor. An effective address adder (24) and a three input adder (26) comprise limit checking logic. The three input adder receives on offse |
| 5784589 |
Distributed free register tracking for register renaming using an availability tracking register |
July 21, 1998 |
| In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages to process instructions for the processor, the processor including a register trans |
| 5777500 |
Multiple clock source generation with independently adjustable duty cycles |
July 7, 1998 |
| Independent functional units are clocked by a clock source generator having at least two adjustable delay lines for independently adjusting the duty cycles of at least two clocks so that speed path margins are individually optimized for each functional unit. |
| 5771365 |
Condensed microaddress generation in a complex instruction set computer |
June 23, 1998 |
| A microarchitecture in a complex instruction computer system is disclosed employing a sparse microROM array and concatenation address circuitry for forming microaddress entry points, avoiding the need for a programmable logic array to translate instruction opcodes and avoiding duplicativ |
| 5764999 |
Enhanced system management mode with nesting |
June 9, 1998 |
| An enhanced system management mode (SMM) includes nesting of SMI (system management interrupt) routines for handling SMI events. Enhanced SMM is implemented in an computer system to support a Virtual System Architecture (VSA) in which peripheral hardware, such as for graphics and/or audi |
| 5752274 |
Address translation unit employing a victim TLB |
May 12, 1998 |
| An address translation unit is disclosed employing a direct-mapped translation lookaside buffer and a relatively small, associative victim translation lookaside buffer for translating linear addresses to physical addresses expediently and avoiding thrashing, without requiring large a |
| 5742755 |
Error-handling circuit and method for memory address alignment double fault |
April 21, 1998 |
| In an .chi.86-compatible processor capable of operating in a protected mode of operation in which privilege levels are assigned to tasks executing therein, an application task being assigned a lowest privilege level and executable in the processor to cause the processor to calculate addr |
| 5742184 |
Microprocessor having a compensated input buffer circuit |
April 21, 1998 |
| An input buffer circuit provides programmable resistors for inputs to a microprocessor and compensates for switching voltage timing differences caused when a selected programmable resistor is utilized for a selected input. In a preferred embodiment, an input buffer circuit has a weak |
| 5740416 |
Branch processing unit with a far target cache accessed by indirection from the target cache |
April 14, 1998 |
| A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. In one embodiment, the BPU includes a target cache and a separate far target cache--the far target cache stores limits |
| 5740410 |
Static clock generator |
April 14, 1998 |
| A processing system includes clock circuitry that statically multiplies/divides a stimulus signal which can then be removed while a resultant product clock is still generated, A cascaded--dual tap delay line is employed having a single phase inversion which is looped back and logical |
| 5740398 |
Program order sequencing of data in a microprocessor with write buffer |
April 14, 1998 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5734881 |
Detecting short branches in a prefetch buffer using target location information in a branch targ |
March 31, 1998 |
| A pipelined x86 processor includes a prefetch unit (prefetch buffer) and a branch unit that cooperate to detect when the target of a branch (designated a short branch) is already in the prefetch buffer, thereby avoiding issuing a prefetch request to retrieve the target. The branch un |
| 5734844 |
Bidirectional single-line handshake with both devices driving the line in the same state for han |
March 31, 1998 |
| Bidirectional handshake protocol circuitry is provided for asserting and deasserting a signal across a single line between a first device and a second device. Only the first device is permitted to assert the signal on the single line; and only the second device is permitted to deassert t |
| 5732253 |
Branch processing unit with target cache storing history for predicted taken branches and histor |
March 24, 1998 |
| A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU implements a branch prediction scheme using a target cache and a separate history cache. The target cache |
| 5732243 |
Branch processing unit with target cache using low/high banking to support split prefetching |
March 24, 1998 |
| A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a target cache organized in banks to support split prefetching. Prefetch requests (addressing a p |
| 5724549 |
Cache coherency without bus master arbitration signals |
March 3, 1998 |
| A method of data communication between asynchronous processes of a computer system is disclosed in connection with a cache coherency system for a processor-cache used in a multi-master computer system in which bus arbitration signals either are not available to the processor-cache, or |
| 5706491 |
Branch processing unit with a return stack including repair using pointers from different pipe s |
January 6, 1998 |
| A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a return stack for call/returns, including return stack pointer repair in the case of the failure |
| 5701448 |
Detecting segment limit violations for branch target when the branch unit does not supply the li |
December 23, 1997 |
| A pipelined 32 bit x86 processor including a prefetch unit and a branch unit. During sequential prefetching, the prefetch unit increments a prefetch physical address PFPA and a corresponding prefetch linear address PFLA--for each prefetch address, the PFLA is compared with the code s |
| 5692168 |
Prefetch buffer using flow control bit to identify changes of flow within the code stream |
November 25, 1997 |
| A prefetch unit includes flow control for controlling the transfer of instruction bytes from a prefetch buffer to a decoder where the prefetch buffer includes predicted change of flow instructions. Instruction bytes in the prefetch buffer are arranged in prefetch blocks--associated with |
| 5689721 |
Detecting overflow conditions for negative quotients in nonrestoring two's complement division |
November 18, 1997 |
| A method of detecting anomalous overflow conditions is used, in an exemplary embodiment, in implementing in a 486-type microprocessor, nonrestoring two's complement division for negative quotients using 2n bit dividends and n bit divisors. Each interative division step, an adder/subt |
| 5689454 |
Circuitry and methodology for pulse capture |
November 18, 1997 |
| Circuitry and methodology for pulse capture employs S-R latch, precharge, and switch circuitries for quickly sensing and capturing a logic pulse from dynamic logic circuitry. The present invention while having general application to any dynamic logic circuitry has particular application |
| 5687202 |
Programmable phase shift clock generator |
November 11, 1997 |
| A programmable phase shift clock generator is disclosed including a phase comparator, an up-down counter, a ring oscillator, and an adjustable delay line for determining a digital signature of an input clock and precisely generating a phase shifted clock signal. |
| 5675528 |
Early detection of overflow and exceptional quotient/remainder pairs for nonrestoring twos compl |
October 7, 1997 |
| A system for the early detection of overflow or exceptional quotient/remainder pairs is used in conjunction with performing nonrestoring division using two's complement 2n bit dividends N and two's complement n bit divisors D--if early overflow is not signaled, and if an exceptional |
| 5664149 |
Coherency for write-back cache in a system designed for write-through cache using an export/inva |
September 2, 1997 |
| A write-back coherency system, including FLUSH/INVAL and LOCK protocols, is used, in an exemplary embodiment, in a microprocessor used in a computer system that selectively provides to the processor FLUSH and INVAL signals to implement a limited write-back protocol. The FLUSH/INVAL proto |
| 5659495 |
Numeric processor including a multiply-add circuit for computing a succession of product sums us |
August 19, 1997 |
| A numeric processor includes a multiply-add circuit with redundant value interface circuitry for performing mathematical function computations as a succession of product sums using redundant binary format values (such as signed digit) as the multiplicand and/or the addend inputs to the |
| 5644788 |
Burst transfers using an ascending or descending only burst ordering |
July 1, 1997 |
| Burst ordering logic is used, in an exemplary embodiment, to implement an ascending only burst ordering for cache line fills in 486 computer systems while maintaining compatibility with the conventional 486 burst ordering which uses both ascending and descending burst orders depending up |
| 5644741 |
Processor with single clock decode architecture employing single microROM |
July 1, 1997 |
| A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memor |
| 5638016 |
Adjustable duty cycle clock generator |
June 10, 1997 |
| An adjustable duty cycle clock generator has first and second delay lines coupled to receive an input clock and cascaded to first and second edge detectors, respectively. The second delay line has a programmable delay and the first and second edge detectors are further coupled to set and |
| 5632037 |
Microprocessor having power management circuitry with coprocessor support |
May 20, 1997 |
| A processing unit includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detecting circuitry detects the assertion of a first signal indicative of a request for suspending operation of the processing unit and the assertion of a second signal indicatin |
| 5630149 |
Pipelined processor with register renaming hardware to accommodate multiple size registers |
May 13, 1997 |
| A microprocessor comprises one or more instruction pipelines having a plurality of stages for processing a stream of instructions, wherein one or more of the instructions reference a defined set of logical registers having multiple addressable sizes as sources and destinations of operand |
| 5630143 |
Microprocessor with externally controllable power management |
May 13, 1997 |
| A processing unit includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the |
| 5617628 |
Integrated circuit extraction tool |
April 8, 1997 |
| An integrated circuit extraction tool for extracting sockets or microprocessors having a staggered pin grid array (SPGA) pin arrangement. Such tool includes an elongated base having a first end and a second end, each end forming a set of teeth that permit entry and extension of the t |
| 5615402 |
Unified write buffer having information identifying whether the address belongs to a first write |
March 25, 1997 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5615113 |
Early signaling of no-overflow for nonrestoring twos complement division |
March 25, 1997 |
| An early no-overflow signaling system and method is used in conjunction with performing nonrestoring division using two's complement 2n bit dividends N and two's complement n bit divisors D--when a no-overflow condition is signaled, a subsequent plurality of iterative partial remaind |
| 5611071 |
Split replacement cycles for sectored cache lines in a 64-bit microprocessor interfaced to a 32- |
March 11, 1997 |
| A procedure for implementing cache line replacement cycle as split replacement cycles is used in a 64/32 computer system including a 64-bit x86 microprocessor interfaced to a 32-bit x86 bus architecture which does not support pipelined bus cycles. The microprocessor includes an internal |
| 5596740 |
Interleaved memory conflict resolution with accesses of variable bank widths and partial return |
January 21, 1997 |
| A shared interleaved memory having a relatively large number of banks employs circuitry and methodology for resolving bank conflicts without significantly inducing delay into the data path. A first and a second port make data read, data write, and instruction fetch requests to/from the |
| 5596735 |
Circuit and method for addressing segment descriptor tables |
January 21, 1997 |
| In a processor having a protected mode of operation in which a computer memory associated with the processor contains global and local descriptor tables addressed by a combination of a base address and an index, the processor having (i) global and local base address registers alternative |
| 5596731 |
Single clock bus transfers during burst and non-burst cycles |
January 21, 1997 |
| A single block bus transfer (SCBT) protocol is implemented, in an exemplary embodiment, in a computer system that includes an .times.86 microprocessor, system logic, and an external memory subsystem including L2 cache and system DRAM, intercoupled by a 586 bus architecture. The micro |
| 5592107 |
Configurable NAND/NOR element |
January 7, 1997 |
| A configurable NAND/NOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The NAND/NOR logic element (FIG. 3, 50) is configurable as either a NAND or a NOR gate by a C (configuration) input (that can be meta |
| 5587666 |
Sense amplifier slew circuitry |
December 24, 1996 |
| A pre-charge load device to pre-charge an input on a sense amplifier is coupled between a positive voltage rail and the input to the sense amplifier and is biased by a bias network coupled between the positive voltage rail and the sense amplifier input to adapt the sense amplifier sl |
| 5584009 |
System and method of retiring store data from a write buffer |
December 10, 1996 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5574672 |
Combination multiplier/shifter |
November 12, 1996 |
| A combination multiplier/shifter circuit (FIG. 2) can be used to implement an arithmetic or execution unit, using the multiplier/shifter to perform both multiplication operations and shift operations (such as for alignment or normalization). The arithmetic unit includes separate multipli |
| 5572682 |
Control logic for a sequential data buffer using byte read-enable lines to define and shift the |
November 5, 1996 |
| Shift-based control logic is used, in an exemplary embodiment, to implement in a microprocessor a circular prefetch queue that stores variable length instructions and transfers four instruction bytes at a time to an instruction decoder. The prefetch queue (10) includes a 16 byte sequenti |
| 5568067 |
Configurable XNOR/XOR element |
October 22, 1996 |
| A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be me |
| 5550499 |
Single delay line adjustable duty cycle clock generator |
August 27, 1996 |
| An adjustable duty cycle clock generator is disclosed having a single delay line cascaded to a multiplexer and first and second edge detectors which respectively drive set and reset inputs on a S-R latch to produce an adjustable duty cycle clock signal. |
| 5524234 |
Coherency for write-back cache in a system designed for write-through cache including write-back |
June 4, 1996 |
| A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DM |
