| Patent Number |
Title Of Patent |
Date Issued |
| 7555664 |
Independent control of core system blocks for power optimization |
June 30, 2009 |
| Power management commands are provided to a power management unit of a processing device, wherein the power management unit coupled to a core system block of the processing device. Sampling of the core system block is performed in response to the power management commands by the power |
| 7539054 |
Method and apparatus to program and erase a non-volatile static random access memory from the bi |
May 26, 2009 |
| A system and method for programming and erasing a semiconductor memory is disclosed. More particularly, the present invention uses the bit lines of a volatile memory portion of semiconductor memory so as to program and erase the non-volatile portion of the semiconductor memory. |
| 7495977 |
Memory system having high-speed row block and column redundancy |
February 24, 2009 |
| A high-speed redundancy circuit having redundant rows/blocks for replacing defective rows, columns and blocks. For row redundancy, an off-pitch encoder in conjunction with row control circuitry is used to disable defective rows while enabling non-defective rows. An off-pitch fuse is |
| 7492195 |
Agile, low phase noise clock synthesizer and jitter attenuator |
February 17, 2009 |
| A phase locked loop circuit, system, and method of operation are provided. The phase-locked loop (PLL) includes a first PLL and a second PLL. The first PLL is nested inside the second PLL. According to one embodiment, the first PLL is coupled to the output of a surface acoustic wave (SAW |
| 7474687 |
Staged correlator |
January 6, 2009 |
| A correlator has a feedback circuit having a first input coupled to an incoming data stream, a second input and an output. A data register is to store an incoming data stream having a number of candidate bits, the data register having an output coupled to the second input of the feedback |
| 7471135 |
Multiplexer circuit |
December 30, 2008 |
| A multiplexer circuit provided herein includes a plurality of pass devices coupled in parallel between a power supply and a ground supply. According to one embodiment, each pass device may include a first pair of transistors, which is coupled in series between the power supply and the |
| 7454645 |
Circuit and method for monitoring the status of a clock signal |
November 18, 2008 |
| A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status ind |
| 7453230 |
Synchronization circuit and method of performing synchronization |
November 18, 2008 |
| The circuit comprises a pulse width modulated (PWM) input signal, a resistor, an instrumentation amplifier, a filter and an analog to digital converter. The method of performing synchronization comprises sampling an analog signal and forming a digital data stream representing the signal, |
| 7447922 |
Supplying power from peripheral to host via USB |
November 4, 2008 |
| A method and system is provided for supplying power to a host via a USB port. The power is transmitted to the host using the standard VBUS and GND lines that are part of standard USB cables and connectors. The peripheral device includes a special USB descriptor block. During the stan |
| 7447254 |
Self-correlating pseudo-noise pairing |
November 4, 2008 |
| A method of transmitting communications codes is used in spread spectrum communications systems. The method includes transmitting a first pseudo-noise code, and transmitting a second pseudo-noise code, wherein the second pseudo-noise code is a time-reversed version of the first pseud |
| 7446063 |
Silicon nitride films |
November 4, 2008 |
| A method of forming structures comprises depositing silicon nitride films simultaneously on a plurality of substrates at a first temperature, and heating the silicon nitride films at a temperature greater than the first temperature. |
| 7439820 |
Reducing the settling time of a crystal oscillator |
October 21, 2008 |
| A method and system for initiating the oscillation of a crystal that controls a crystal oscillator by applying an initiating pulse to said crystal. The initiating pulse having a pulse width less than one half the periodicity of said crystal. |
| 7433439 |
Apparatus, system, and method for synchronizing signals received by one or more system component |
October 7, 2008 |
| A phase shift apparatus, system and method are described herein for synchronizing output signals upon one or more components of a synchronous system. In one embodiment, the phase shift apparatus may be implemented as a clock generation circuit, which is configured to provide synchronous |
| 7433348 |
Time division multiplexing protocol for wireless networks |
October 7, 2008 |
| A multi-node time division multiplexing (TDM) system is disclosed. The improved method and apparatus utilizes an asynchronous synchronization packet (ASP) to synchronize the timing in all the nodes of the system. In some embodiments, the ASP also maps the time slots in a data frame to |
| 7432749 |
Circuit and method for improving frequency range in a phase locked loop |
October 7, 2008 |
| A circuit and method for providing a periodic clock signal, such as a high frequency clock signal. In one example, the circuit may include a phase locked loop circuit having a voltage controlled oscillator, the voltage controlled oscillator having a voltage input, a calibration input, an |
| 7409616 |
Built in self test system and method for detecting and correcting cycle slip within a deserializ |
August 5, 2008 |
| A system and method are provided for built-in-self test of any bits that have slipped from their appropriate positions within a frame character clock cycle. If a bit has slipped, then the built-in-self test mechanism can also implement either a clock generation stretch operation or a |
| 7409027 |
System and method for recovering a clock using a reduced rate linear phase detector and voltage |
August 5, 2008 |
| An improved clock recovery system, phase-locked loop, and phase detector are provided as well as a method for generating charge pump signals. The clock recovery system includes a phase-locked loop. The phase-locked loop includes a phase detector and a voltage-controlled oscillator. The p |
| 7408827 |
Pulse generation scheme for improving the speed and robustness of a current sense amplifier with |
August 5, 2008 |
| Disclosed herein is a current sense amplifier (ISA) circuit with increased speed, less insensitivities to process variation, better stability and improved output signal swing. According to one embodiment, the ISA circuit described herein may include a pair of output nodes and a first |
| 7406572 |
Universal memory circuit architecture supporting multiple memory interface options |
July 29, 2008 |
| An architecture for an improved non-volatile memory device supporting multiple memory interface options is disclosed herein. In one embodiment, the improved memory device includes a magnetic random access memory (MRAM) array and at least one memory interface block, which is configured |
| 7405987 |
Low voltage, high gain current/voltage sense amplifier with improved read access time |
July 29, 2008 |
| A low voltage, high-gain current/voltage sense amplifier (ISA/VSA) circuit with improved read access time is provided herein. According to one embodiment, the ISA/VSA described herein includes a pair of current reference branches for generating a pair of reference currents in respons |
| 7405629 |
Frequency modulator, circuit, and method that uses multiple vector accumulation to achieve fract |
July 29, 2008 |
| A frequency synthesizer is provided having a fractional-N control circuit and method. The control circuit can operate as having a modulator that selectively applies any fractional ratio to a frequency divider within, for example, a feedback loop of a PLL. The modulator can be a delta-sig |
| 7395366 |
System, method, and apparatus for connecting USB peripherals at extended distances from a host c |
July 1, 2008 |
| An apparatus, method, and system for coupling a host computer to a peripheral device over an extended distance. In one example, a first hub is provided for coupling with the host computer, the first hub configured as a compound device including a hub function and an embedded function, |
| 7394308 |
Circuit and method for implementing a low supply voltage current reference |
July 1, 2008 |
| A circuit for generating a reference current, comprising a positive feedback loop, a negative feedback loop, and a floating current mirror coupled to the positive feedback loop. The negative feedback loop may operate to divert current directly from the floating mirror, and may also o |
| 7394293 |
Circuit and method for rapid power up of a differential output driver |
July 1, 2008 |
| Output driver circuits and related methods. In one example, the output driver circuit includes a translator for converting the single ended data input signal into a pair of signals; a set of output transistors selectively controlled by the pair of signals; a cascode current source fo |
| 7390750 |
Method of patterning elements within a semiconductor topography |
June 24, 2008 |
| A method is provided which includes forming a hardmask feature adjacent to a patterned sacrificial structure of a semiconductor topography, selectively removing the patterned sacrificial structure to expose a lower layer and etching exposed portions of the lower layer in alignment wi |
| 7388440 |
Circuit and method to speed up PLL lock-time and prohibit frequency runaway |
June 17, 2008 |
| A lock-aid circuit and method is applied to a phase lock loop (PLL) having a voltage controlled oscillator (VCO), wherein the lock aid is coupled with the input of the VCO. In one example, the lock aid includes a Schmitt trigger having an output, a switch having an output and an input |
| 7379375 |
Memory circuits having different word line driving circuit configurations along a common global |
May 27, 2008 |
| Memory circuits having different configurations of local word line driving circuits (LWLDC) and methods for designing such circuits are provided. The memory circuits include an array of memory cells and a plurality of local word lines each coupled to a different subset of the array of |
| 7369090 |
Ball Grid Array package having integrated antenna pad |
May 6, 2008 |
| An apparatus for an improved Ball Grid Array (BGA) package includes a semiconductor device having a radio frequency (RF) input or output, an antenna pad, and a BGA package structured to house the semiconductor device and the antenna pad. The antenna pad may be coupled to the radio fr |
| 7368960 |
Circuit and method for monitoring the integrity of a power supply |
May 6, 2008 |
| Circuits and methods are provided herein for monitoring the integrity of a power supply, the circuits and methods providing additional resources/information for diagnosing a cause behind a reset signal, and in some cases, a reason behind a power failure. A first method described here |
| 7365403 |
Semiconductor topography including a thin oxide-nitride stack and method for making the same |
April 29, 2008 |
| A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon |
| 7362163 |
Flyback capacitor level shifter feedback regulation for negative pumps |
April 22, 2008 |
| Systems and methods of flyback capacitor level shifter feedback regulation for negative pumps. In accordance with a first embodiment of the present invention, a feedback regulator for a negative output charge pump comprises a flyback capacitor for inverting an output of the negative |
| 7359407 |
Data interface that is configurable into separate modes of operation for sub-bit de-skewing of p |
April 15, 2008 |
| A data interface is provided that can de-skew data signals by taking into account different skewing effects on each data signal. The data interface can be used, for example, in a communication system and can be configured to operate in one of three possible modes of operation. In the fir |
| 7356635 |
Compressed report descriptors for USB devices |
April 8, 2008 |
| A method and apparatus for creating USB peripheral device report descriptors: A short, compressed, report descriptor is stored in a peripheral device. This short report descriptor is transmitted to a USB wireless bridge and combined with templates stored in the bridge to create a USP |
| 7355489 |
High gain, high frequency CMOS oscillator circuit and method |
April 8, 2008 |
| An oscillator amplifier circuit is provided. The amplifier circuit can be used with a resonator to amplify and form a resonating oscillator. The amplifier circuit comprises an active circuit which includes an inverter and a current-controlled biasing circuit. One transistor of the invert |
| 7352444 |
Method for arranging and rotating a semiconductor wafer within a photolithography tool prior to |
April 1, 2008 |
| A method for arranging a semiconductor wafer within a photolithography tool and methods for processing a semiconductor wafer employing such an arrangement process are provided. The arrangement process includes positioning a semiconductor wafer on a stage in a pre-alignment unit of a |
| 7349190 |
Resistor-less accurate low voltage detect circuit and method for detecting a low voltage conditi |
March 25, 2008 |
| A low voltage detect circuit is provided herein for detecting when an external voltage (Vext) drops below a predetermined minimum voltage. In general, the low voltage detect circuit described herein may be configured to detect a low voltage condition based on a threshold voltage diff |
| 7346849 |
Executable code derived from user-selectable links embedded within the comments portion of a pro |
March 18, 2008 |
| An apparatus, computer program, and method are disclosed for generating computer executable code. The code is compiled from a data set, and the data set is compiled by selecting a link within a comments portion of a text editor portion of a program. The data set can then be inserted into |
| 7346724 |
Enabling multiple ATA devices using a single bus bridge |
March 18, 2008 |
| Embodiments of the invention include a bus bridge that is capable of communicating with more than one MSC device coupled to it. In some embodiments, the bridge includes a LUN processor that translates different LUN numbers received from the bus into different addresses and LUNs for d |
| 7330389 |
Address detection system and method that compensates for process, temperature, and/or voltage fl |
February 12, 2008 |
| An address transition detector (ATD) system is provided with an integrator, a feedback circuit and an output circuit. The integrator has an enhanced architecture that ensures a fast output signal switching, low power consumption during the integration time, fast output transition at |
| 7329934 |
Smooth metal semiconductor surface and method for making the same |
February 12, 2008 |
| A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the |
| 7327199 |
Phase-locked loop (PLL) device and method for entering a test mode without a dedicated test pin |
February 5, 2008 |
| According to one embodiment, a phase-locked loop (PLL) device includes test circuitry for entering/exiting a test mode upon receiving a particular pulse train at a reference clock input of the PLL. In addition, exemplary methods are provided herein for entering a test mode and detect |
| 7327114 |
Fan control utilizing bi-directional communications |
February 5, 2008 |
| A system and method for bi-directional communication between a system controller and a fan controller: The system operates in two modes and there are two communication paths between the system controller and the fan controller. The first communication path provides a PWM signal the f |
| 7295051 |
System and method for monitoring a power supply level |
November 13, 2007 |
| A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level |
| 7280574 |
Circuit for driving a laser diode and method |
October 9, 2007 |
| A circuit for driving a laser diode has a variable bias circuit. The variable bias circuit has an output designed to couple to the laser diode. A modulation circuit has an output designed to couple to the laser diode. |
| 7279981 |
Compensation method for low voltage, low power unity gain amplifier |
October 9, 2007 |
| A unity gain amplifier has a current mirror. A compensation circuit has an input coupled to an output of the current mirror. An output transistor has a base coupled to the output of the current mirror and a source of the output transistor is coupled to an output of the compensation c |
| 7279925 |
Capacitive feedforward circuit, system, and method to reduce buffer propagation delay |
October 9, 2007 |
| A buffer circuit, system, and method are provided. The buffer circuit includes a control circuit coupled to an output of the buffer, or possibly to an output of the first stage of a buffer. A pre-charge circuit is also provided coupled to bias an input of the control circuit to a vol |
| 7275119 |
Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-perf |
September 25, 2007 |
| A bus architecture includes master devices that are each capable of initiating a data transfer procedure by generating a bus request signal. Each of the master devices is arranged to transmit an address signal to an address input of a multiplexer, to transmit a data signal to a data |
| 7264975 |
Metal profile for increased local magnetic fields in MRAM devices and method for making the same |
September 4, 2007 |
| A method for fabricating a magnetic random access memory circuit (MRAM) and a MRAM circuit resulting therefrom are provided. The method includes depositing a first conductive layer upon and in contact with a plurality of magnetic cell junctions and selectively removing portions of the fi |
| 7253094 |
Methods for cleaning contact openings to reduce contact resistance |
August 7, 2007 |
| A method for processing a semiconductor topography which includes removing metal oxide layers from the bottom of contact openings is provided. In some embodiments, the method may include etching openings within a dielectric layer to expose conductive and silicon surfaces within the s |
| 7245725 |
Dual processor framer |
July 17, 2007 |
| A dual processor framer includes a receiver and a transmitter which share common circuitry and/or code. Separate direct memory access controllers may be used for each of the receiver and transmitter. Processing is distributed over two or more processors. One processor may be a lower |
