A coprocessor system is disclosed in which a CPU in a game machine body and a CPU in a game cartridge are formed by CPU cores having the same architecture and memory mapping functions. The cycle time of a second CPU, for example the CPU in the game cartridge, is shorter than the cycle ti
A variable bit-length code processing circuit includes first, second and third registers (12, 20, 22) each of which is of 1 word, and memory data is loaded to the first register (12), and a variable bit-length code is withdrawn from the third register (22). The second register (20) and t
