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Cray Inc. Patents
Assignee:
Cray Inc.
Address:
Seattle, WA
No. of patents:
132
Patents:


1 2 3










Patent Number Title Of Patent Date Issued
D481040 Panel for a system chassis October 21, 2003
D481035 System chassis October 21, 2003
8583898 System and method for managing processor-in-memory (PIM) operations November 12, 2013
A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for operations that are vectorizable. The vectorizable operations are examined to determine wh
8296771 System and method for mapping between resource consumers and resource providers in a computing s October 23, 2012
A system and method for allocating system resources is described herein. In one embodiment, the method comprises creating, in a computer system, a resource consumer and assigning the resource consumer one of a set of flavors. The method further includes determining whether the resource
8286135 Performance visualization including hierarchical display of performance data October 9, 2012
Systems and methods provide a display indicating performance characteristics of a computer application. The display may include a call graph having nodes that represent subunits of the application. A first set of statistics for the subunit may be represented in the size or dimensions
8261134 Error management watchdog timers in a multiprocessor computer September 4, 2012
A multiprocessor computer system comprises one or more watchdog timers operable to detect failure of a memory operation based on passage of a certain timing period from a memory operation being issued without a valid response. An error handler is operable to take corrective action re
8245087 Multi-bit memory error management August 14, 2012
Various embodiments include fault tolerant memory apparatus, methods, and systems, including an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit
8239704 Global clock via embedded spanning tree August 7, 2012
In some embodiments, the present invention relates to a method of maintaining a global clock within a multiprocessor system having a plurality of nodes that are connected in a network via links. A virtual spanning tree is mapped onto the network and the nodes and the links are config
8184626 High-radix interprocessor communications system and method May 22, 2012
A high-radix interprocessor communications system and method having a plurality of processor nodes, a plurality of first routers and a plurality of second routers. Each first router is connected to a processor node and to two or more second routers. Each first router includes input p
8170724 Systems and associated methods for controllably cooling computer components May 1, 2012
Computer systems and associated methods for cooling computer components are disclosed herein. One embodiment of a computer system includes a computer cabinet having an air inlet spaced apart from an air outlet. The computer system also includes heat exchangers positioned in the computer
8126674 Memory-daughter-card-testing method and apparatus February 28, 2012
A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and c
8095759 Error management firewall in a multiprocessor computer January 10, 2012
A multiprocessor computer system comprises a plurality of processors and a plurality of nodes, each node comprising one or more processors. A local memory in each of the plurality of nodes is coupled to the processors in each node, and a hardware firewall comprising a part of one or
8081459 Air conditioning systems for computer systems and associated methods December 20, 2011
Computer systems with air cooling systems and associated methods are disclosed herein. In several embodiments, a computer system can include a computer cabinet holding multiple computer modules, and an air mover positioned in the computer cabinet. The computer system can also include
8065573 Method and apparatus for tracking, reporting and correcting single-bit memory errors November 22, 2011
Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counter
8051338 Inter-asic data transport using link control block manager November 1, 2011
An apparatus includes a SerDes circuit and a link control block (LCB). The SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane. A SerDes lane includes the SerDes circuit pair coupled by a communications medium. The LCB includes an error tracking circuit and a cont
8024638 Apparatus and method for memory read-refresh, scrubbing and variable-rate refresh September 20, 2011
A memory controller and method that provide a read-refresh (also called "distributed-refresh") mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent r
7984453 Event notifications relating to system failures in scalable systems July 19, 2011
An availability system is provided that includes a hierarchy of controllers for providing event notifications relating to availability of components of a scalable MPP system. A controller receives a subscription from a child controller that identifies an event type and a generator. T
7974052 Method and apparatus for switched electrostatic discharge protection July 5, 2011
One embodiment includes an integrated circuit including an input circuit, a first diode including a first anode and a first cathode, with the first cathode coupled to a first voltage, the first anode coupled to the input circuit at a node via a first mechanical switch, a second diode inc
7966591 System and method for verifying race-driven registers June 21, 2011
Embodiments include a system and method for generating RTL description of an electronic device provided for a design test and a test bench environment to drive stimulus into the electronic device, identifying at least one register to be verified during the design test, authoring a pr
7957412 Lonely pulse compensation June 7, 2011
An apparatus comprising a transmission line, a receiver circuit, and a high pass filter circuit coupled between the transmission line and a receiver circuit input. The receiver circuit is configured to receive a data signal over the transmission line at a first data rate. The high pa
7904685 Synchronization techniques in a multithreaded environment March 8, 2011
Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in
7903403 Airflow intake systems and associated methods for use with computer cabinets March 8, 2011
Airflow intake systems for use with computer cabinet air conditioning systems are disclosed herein. In one embodiment, a computer system includes a plurality of computer modules and an associated air mover positioned in an interior portion of a computer cabinet. The computer cabinet
7898799 Airflow management apparatus for computer cabinets and associated methods March 1, 2011
Airflow management apparatuses for computer cabinets and associated methods are disclosed herein. The computer cabinets include a plurality of computer modules positioned between an air inlet and an air outlet and an air mover configured to move a flow of cooling air from the air inlet,
7890673 System and method for accessing non processor-addressable memory February 15, 2011
A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial cabinet-to-cabine
7864792 Load balancing for communications within a multiprocessor computer system January 4, 2011
In a system having a N output ports, wherein N is an integer greater than one, a method of distributing packets across the plurality of output ports. A packet having two or more fields is received and a first number is computed as a function of one or more of the plurality of fields. A
7852836 Reduced arbitration routing system and method December 14, 2010
A system and method for routing packets from one node to another node in a system having a plurality of nodes connected by a network. A node router is provided in each node, wherein the node router includes a plurality of network ports, including a first and a second network port, wherei
7843929 Flexible routing tables for a high-radix router November 30, 2010
A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a column, computing a
7830905 Speculative forwarding in a high-radix router November 9, 2010
A system and method for speculative forwarding of packets received by a router, wherein each packet includes phits and wherein one or more phits include a cyclic redundancy code (CRC). A packet is received and phits of the packet are forwarded to router logic. A cyclic redundancy code fo
7826996 Memory-daughter-card-testing apparatus and method November 2, 2010
A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and c
7793073 Method and apparatus for indirectly addressed vector load-add-store across multi-processors September 7, 2010
A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, one vector registe
7764629 Identifying connected components of a graph in parallel July 27, 2010
A method and system for finding connected components of a graph using a parallel algorithm is provided. The connected nodes system performs a search algorithm in parallel to identify subgraphs of the graph in which the nodes of the subgraph are connected. The connected nodes system also
7757497 Method and apparatus for cooling electronic components July 20, 2010
A spray cooling system includes a spray delivery device and a cooling liquid delivered to the spray delivery device. The spray delivery device includes one or more inlet apertures and one or more corresponding outlet apertures, at least one pair of inlet aperture and corresponding outlet
7751519 Phase rotator for delay locked loop based SerDes July 6, 2010
An apparatus comprising a first multiplexer circuit (MUX) to receive a plurality of clock phase signals at a corresponding plurality of MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a phase delay circuit to receive the
7743223 Decoupling of write address from its associated write data in a store to a shared memory in a mu June 22, 2010
In a computer system having a plurality of processors connected to a shared memory, a system and method of decoupling an address from write data in a store to the shared memory. A write request address is generated for a memory write, wherein the write request address points to a mem
7739667 Parallelism performance analysis based on execution trace information June 15, 2010
A system for conducting performance analysis for executing tasks. The analysis involves generating a variety of trace information related to performance measures, including parallelism-related information, during execution of the task. In order to generate the trace information, target
7735088 Scheduling synchronization of programs running as streams on multiple processors June 8, 2010
Systems and methods start a process in an operating system. Additionally, a plurality of program units associated with the process are started. When a context shifting event occurs, each of the plurality of program units has their scheduling synchronized and their context set so that
7676728 Apparatus and method for memory asynchronous atomic read-correct-write operation March 9, 2010
A memory controller and method that provide a read-refresh (also called "distributed-refresh") mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent r
7630198 Multi-stage air movers for cooling computer systems and for other uses December 8, 2009
Multi-stage air movers for cooling computers and other systems are described herein. In one embodiment, a computer system includes a computer cabinet holding a plurality of computer modules. The computer cabinet includes an air inlet and an air outlet. The computer system further inc
7624246 Method and system for memory allocation in a multiprocessing environment November 24, 2009
A method and system for allocating and de-allocating memory for threads of an application is provided. An allocation system provides a heap for tracking free tokens of memory that are available for allocation to threads of an application. A heap tracks collections of free tokens of t
7587305 Transistor level verilog September 8, 2009
A method includes specifying a first set of interconnected devices associated with a first leaf cell in Verilog syntax, and specifying a second set of interconnected devices associated with a second leaf cell in Verilog syntax. A connection between the first leaf cell and the second
7584332 Computer systems with lightweight multi-threaded architectures September 1, 2009
Embodiments of the present invention provide a class of computer architectures generally referred to as lightweight multi-threaded architectures (LIMA). Other embodiments may be described and claimed.
7577816 Remote translation mechanism for a multinode system August 18, 2009
The present invention provides a method of initializing shared memory in a multinode system. The method includes building a local address space in each of a plurality of nodes and exporting the local address space from each of the plurality of nodes to a Remote Translation Table (RTT) in
7565593 Apparatus and method for memory bit-swapping-within-address-range circuit July 21, 2009
A memory controller and method that provide a read-refresh (also called "distributed-refresh") mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent r
7558910 Detecting access to a memory location in a multithreaded environment July 7, 2009
Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in
7558889 Accessing a collection of data items in a multithreaded environment July 7, 2009
Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in
7543133 Latency tolerant distributed shared memory multiprocessor computer June 2, 2009
A computer system having low memory access latency. In one embodiment, the computer system includes a network and one or more processing nodes connected via the network, wherein each processing node includes a plurality of processors and a shared memory connected to each of the proce
7536690 Deferred task swapping in a multithreaded environment May 19, 2009
A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single p
7533460 Method for partitioning banks of processors in large computer systems May 19, 2009
Systems and methods for operatively connecting processor banks in large computer systems are disclosed herein. In one embodiment, a computer system includes a first bank of processors, a second bank of processors spaced apart from the first bank of processors, and a connector assembly
7519771 System and method for processing memory instructions using a forced order queue April 14, 2009
A novel system and method for processing memory instructions. One embodiment of the invention provides a method for processing a memory instruction. In this embodiment, the method includes obtaining a memory request; storing the memory request in an Initial Request Queue (IRQ); and p
7478769 Method and apparatus for cooling electronic components January 20, 2009
A spray cooling system includes a spray delivery device and a cooling liquid delivered to the spray delivery device. The spray delivery device includes one or more inlet apertures and one or more corresponding outlet apertures, at least one pair of inlet aperture and corresponding outlet
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