| Patent Number |
Title Of Patent |
Date Issued |
| 6624017 |
Manufacturing process of a germanium implanted HBT bipolar transistor |
September 23, 2003 |
| A process fabricates a vertical structure high carrier mobility transistor on a substrate of crystalline silicon doped with impurities of the N type, the transistor having a collector region located at a lower portion of the substrate. The process includes: defining a window in the semic |
| 6566690 |
Single feature size MOS technology power device |
May 20, 2003 |
| A MOS technology power device includes a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating |
| 6424957 |
Method and apparatus for parallel processing of fuzzy rules |
July 23, 2002 |
| Method and apparatus of parallel processing of multiple inference rules organized in fuzzy sets or logical functions of multiple fuzzy sets including membership functions defined in a so-called universe of discourse. The inference rules are configured essentially as IF-THEN rules wit |
| 6218228 |
DMOS device structure, and related manufacturing process |
April 17, 2001 |
| A DMOS device structure includes a lightly doped semiconductor layer of a first conductivity type, a plurality of lightly doped semiconductor regions of a second conductivity type extending from a top surface of the lightly doped semiconductor layer thereinto, source regions of the first |
| 6199056 |
Apparatus for dividing an integer by 2n with over or under approximation |
March 6, 2001 |
| An apparatus over or under approximates the result of dividing a binary number representing an integer 2.sup.n. The division by 2.sup.n is performed by truncating the n least significant bits of the integer. In order to over or under approximate the result, the nth truncated bit, i.e |
| 6188998 |
Method and apparatus for storing one or more natural membership functions |
February 13, 2001 |
| In a method, according to the invention, of storing one or more natural membership functions of respectively one or more natural variables being each defined within a natural universe of discourse having a lowest natural value and a highest natural value, the natural membership funct |
| 6168981 |
Method and apparatus for the localized reduction of the lifetime of charge carriers, particularl |
January 2, 2001 |
| A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrate |
| 6140679 |
Zero thermal budget manufacturing process for MOS-technology power devices |
October 31, 2000 |
| A zero thermal budget manufacturing process for a MOS-technology power device. The method comprises the steps of: forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type; removing the insulated gate layer from se |
| 6127847 |
High-speed bipolar-to-CMOS logic converter circuit |
October 3, 2000 |
| A high-speed bipolar-to-CMOS logic converter circuit, including an input stage, including a differential amplifier meant to be connected to a bipolar-logic circuit portion and to be supplied by the supply voltage of the bipolar-logic portion, and an output stage, which is supplied by the |
| 6111297 |
MOS-technology power device integrated structure and manufacturing process thereof |
August 29, 2000 |
| A MOS-technology power device integrated structure includes a first plurality of elongated doped semiconductor stripes of a first conductivity type formed in a semiconductor layer of a second conductivity type, each including an elongated source region of the first conductivity type, an |
| 6064087 |
Single feature size MOS technology power device |
May 16, 2000 |
| A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulatin |
| 6061672 |
Fuzzy logic neural network modular architecture |
May 9, 2000 |
| The invention relates to a modular architecture of a cellular network for improved large-scale integration, of the type which comprises a plurality of fuzzy cellular elements (C.sub.m,n) interconnected to form a matrix of elements having at least m rows and n columns, the row and column |
| 6054737 |
High density MOS technology power device |
April 25, 2000 |
| A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulati |
| 6051933 |
Bipolar power device having an integrated thermal protection for driving electric loads |
April 18, 2000 |
| A monolithically integrated power device for driving electrical loads includes a power stage having a high-voltage bipolar transistor and a low-voltage auxiliary transistor cascade-connected and inserted between a first power supply terminal and a second power supply terminal of the |
| 6051862 |
MOS-technology power device integrated structure |
April 18, 2000 |
| A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the s |
| 6047276 |
Cellular neural network to implement the unfolded Chua's circuit |
April 4, 2000 |
| A neural cellular network for implementing a so-called Chua's circuit, and comprising at least first, second and third cells having respective first and second input terminals and respective state terminals, the first and second input terminals being to receive a first and a second refer |
| 6033947 |
Driving circuit for electronic semiconductor devices including at least a power transistor |
March 7, 2000 |
| The invention relates to a control circuit for semiconductor devices which is formed on a substrate (1) doped by a first dopant type, the integrated circuit comprising a first epitaxial layer (2) grown on the substrate (1) and doped by the first dopant type, and an isolation well (3) dop |
| 6030888 |
Method of fabricating high-voltage junction-isolated semiconductor devices |
February 29, 2000 |
| A method of fabricating a junction-isolated semiconductor device is provided which includes the following steps. Within a first P-type buried region second N-type buried regions are formed. Over the first and second buried regions, an N-type epitaxial layer defining a surface of the devi |
| 6030870 |
High density MOS technology power device |
February 29, 2000 |
| A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulati |
| 6001705 |
Process for realizing trench structures |
December 14, 1999 |
| A process for forming, on a semiconductor substrate, an isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of:defining an isolation region on a layer of silicon o |
| 5986323 |
High-frequency bipolar transistor structure |
November 16, 1999 |
| A high-frequency bipolar transistor structure includes a base region of a first conductivity type formed in a silicon layer of a second conductivity type, the base region comprising an intrinsic base region surrounded by an extrinsic base region, an emitter region of the second conductiv |
| 5985721 |
Single feature size MOS technology power device |
November 16, 1999 |
| A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulatin |
| 5963065 |
Low offset push-pull amplifier |
October 5, 1999 |
| A low offset amplifier has an output stage constituted by an npn transistor and a pnp transistor in a push-pull arrangement, and a driver stage. The latter includes a current-mirror circuit having, in its input branch, a pnp transistor in series with a first constant-current generator an |
| 5945819 |
Voltage regulator with fast response |
August 31, 1999 |
| The invention relates to a voltage regulator connected between first and second voltage references and having an output terminal for delivering a regulated output voltage. The voltage regulator includes at least one voltage divider, connected between the output terminal and the second |
| 5943664 |
Memory and method for storing membership functions using vertices and slopes |
August 24, 1999 |
| Memory and storage method in an electronic controller operating with fuzzy logic procedures for membership functions (FA) of logical variables (M) defined in a so-called discourse universe (U) discretized at a finite number of points (m) which provide memorization of triangular or trapez |
| 5939769 |
Bipolar power transistor with high collector breakdown voltage and related manufacturing process |
August 17, 1999 |
| There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate of the N type, over which a lightly doped N type layer, constituting a collector region of the transistor, is superimposed. The transistor has a base region comp |
| 5933733 |
Zero thermal budget manufacturing process for MOS-technology power devices |
August 3, 1999 |
| A zero thermal budget manufacturing process for a MOS-technology power device. The method comprises the steps of: forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type; removing the insulated gate layer from se |
| 5915247 |
Method for storing membership functions and related circuit for calculating a grade of membershi |
June 22, 1999 |
| A method for storing a membership function, include storing a position of a vertex of a triangle that defines the membership function in a universe of discourse and storing a first distance between the position of the vertex a point of intersection between a left side of the triangle and |
| 5914642 |
Temperature independent current controlled multivibrator |
June 22, 1999 |
| A current-controlled multivibrator having increased accuracy independent of variations in process and temperature. The oscillator employs a bandgap voltage in combination with a current generator to ensure operational stability despite temperature and process variations. |
| 5900662 |
MOS technology power device with low output resistance and low capacitance, and related manufact |
May 4, 1999 |
| A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body regi |
| 5900652 |
Apparatus for the localized reduction of the lifetime of charge carriers, particularly in integr |
May 4, 1999 |
| A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrate |
| 5895249 |
Integrated edge structure for high voltage semiconductor devices and related manufacturing proce |
April 20, 1999 |
| An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first, lightly doped ring of the |
| 5888889 |
Integrated structure pad assembly for lead bonding |
March 30, 1999 |
| A process for manufacturing an integrated structure pad assembly for wire bonding to a power semiconductor device chip including a chip portion having a top surface covered by a metallization layer which has a first sub-portion wherein functionally active elements of the power device are |
| 5886381 |
MOS integrated device comprising a gate protection diode |
March 23, 1999 |
| The device presents a polysilicon layer extending over a wafer of semiconductor material, along the edge of the active region of the device, and partly over a thick field oxide layer which externally delimits the active region. The polysilicon layer forms both a field-plate region at |
| 5883412 |
Low gate resistance high-speed MOS-technology integrated structure |
March 16, 1999 |
| A high-speed MOS-technology power device integrated structure includes a plurality of elementary functional units formed in a lightly doped semiconductor layer of a first conductivity type, the elementary functional units including channel regions of a second conductivity type covere |
| 5880628 |
High-efficiency voltage booster circuit operating at very low supply voltage |
March 9, 1999 |
| A voltage booster circuit including a pull-up capacitor connected to the supply line via a PMOS switching transistor. The other terminal of the pull-up capacitor is supplied with a pull-up voltage switching between a first value determining charging of the capacitor, and a second value |
| 5875438 |
Method for storing membership functions and related circuit for calculating a grade of membershi |
February 23, 1999 |
| A method for storing a membership function, include storing a position of a vertex of a triangle that defines the membership function in a universe of discourse and storing a first distance between the position of the vertex a point of intersection between a left side of the triangle and |
| 5874338 |
MOS-technology power device and process of making same |
February 23, 1999 |
| A MOS-technology power device including a semiconductor material layer of a first conductivity type having a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type and a heavily d |
| 5869357 |
Metallization and wire bonding process for manufacturing power semiconductor devices |
February 9, 1999 |
| A metallization and bonding process for manufacturing a power semiconductor device includes a step of depositing a first metal layer over the entire surface of a chip; a step of selectively etching of the first metal layer to form desired patterns of metal interconnection lines between c |
| 5866461 |
Method for forming an integrated emitter switching configuration using bipolar transistors |
February 2, 1999 |
| A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each othe |
| 5856701 |
Dielectrically isolated power semiconductor devices |
January 5, 1999 |
| Semiconductor device chips having a first layer of semiconductor material, a second layer of a semiconductor material and an insulating layer disposed therebetween. The first layer of semiconductor material has doped semiconductor regions disposed therein, and the second layer of sem |
| 5854506 |
Semiconductor particle-detector |
December 29, 1998 |
| A particle-detector is formed on a die of semiconductor material (20) comprising: first and second layers (22, 23) with a first type of conductivity (N), a third layer (21) with a second type of conductivity (P), interposed between the first and second layers (22, 23), first and seco |
| 5852382 |
Three-state CMOS output buffer circuit |
December 22, 1998 |
| A three-state CMOS output buffer circuit includes a final amplifier stage having a pull-up transistor and a pull-down transistor connected between a voltage supply and ground and having a common output node, and a control circuitry for driving the final amplifier stage including a first |
| 5851855 |
Process for manufacturing a MOS-technology power device chip and package assembly |
December 22, 1998 |
| A process for manufacturing a MOS-technology power device chip and package assembly, the MOS-technology power device chip comprises a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functional unit contributing a respective |
| 5841167 |
MOS-technology power device integrated structure |
November 24, 1998 |
| A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the s |
| 5838042 |
DMOS device structure, and related manufacturing process |
November 17, 1998 |
| A DMOS device structure includes a lightly doped semiconductor layer of a first conductivity type, a plurality of lightly doped semiconductor regions of a second conductivity type extending from a top surface of the lightly doped semiconductor layer thereinto, source regions of the first |
| 5828244 |
Driving circuit and method for driving a MOS transistor with delayed activation |
October 27, 1998 |
| A driver circuit delays the turning on of a MOS transistor by utilizing the time-wise pattern of the circuit input signal rather than generating a delay within the circuit itself. A threshold type of circuit element is arranged so that no current flows toward or from, depending on the ty |
| 5821616 |
Power MOS device chip and package assembly |
October 13, 1998 |
| A power MOS chip and package assembly is provided for packaging a power MOS chip that has high heat dissipation. The assembly maintains a low contact resistance to the chip using compression without damaging the chip. The package assembly includes a thermally conductive body, a chip, an |
| 5817546 |
Process of making a MOS-technology power device |
October 6, 1998 |
| A process forms a MOS-technology power device including a semiconductor material layer of a first conductivity type and a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type |
| 5809486 |
Fuzzy processing method and a processor implementing the same |
September 15, 1998 |
| This invention relates to a fuzzy processor having an input X for at least a plurality of input variables X-i and an output U for one or more output results U-k, and including a fuzzyfication unit FU having an input coupled to the input X, a fuzzy rule processing unit RU having an input |
