| Patent Number |
Title Of Patent |
Date Issued |
| RE40106 |
Calibration of isolated analog-to-digital converters |
February 26, 2008 |
| Measurement data collected by isolated ADCs in multiple channels may be related. In such a scenario, data may be transmitted to a microcontroller or programmable logic device for centralized processing. Gain and offset of the ADCs in different channels, particularly their drift relative |
| 7619476 |
Biasing stage for an amplifier |
November 17, 2009 |
| An amplifier biasing stage includes a transistor that provides a biasing signal for a complementary pair of field-effect transistors included in an output stage of an amplifier. The amplifier biasing stage also includes one resistive element connected to an emitter of the transistor, |
| 7616089 |
Compensation of field effect on polycrystalline resistors |
November 10, 2009 |
| A resistive circuit includes a first terminal and a second terminal and polycrystalline first and second resistive segments coupled between the first and second terminals. A third terminal A is coupled to the first resistive segment, and a third terminal B is coupled to the second re |
| 7613311 |
Digital implementation of a fourth order Linkwitz-Riley network with a low cutoff frequency |
November 3, 2009 |
| A simplified digital implementation of a fourth order Linkwitz-Riley crossover network is provided using approximations and transformations of the classical form. The approximation is particularly beneficial when the crossover frequency is low relative to the digital sampling rate, such |
| 7606380 |
Method and system for sound beam-forming using internal device speakers in conjunction with exte |
October 20, 2009 |
| A method and system for sound beam-forming using internal device speakers in conjunction with external speakers provides a low cost alternative to present external surround array systems. A processing circuit within an audio device or audio/visual (AV) device such as a digital television |
| 7606377 |
Method and system for surround sound beam-forming using vertically displaced drivers |
October 20, 2009 |
| A method and system for surround sound beam-forming using vertically displaced drivers provides a low cost alternative to present external surround array systems. A pair of vertically displaced speaker drivers is supplied with surround and main channel information in a controlled phase |
| 7605723 |
Circuits and methods for implementing mode selection in multiple-mode integrated circuits |
October 20, 2009 |
| Mode selection circuitry selects one of a plurality of operational modes supported by an integrated circuit by detecting a selected connection between a first terminal of the integrated circuit and a mode control terminal of the integrated circuit. Other including a mode control term |
| 7599462 |
Hybrid analog/digital phase-lock loop with high-level event synchronization |
October 6, 2009 |
| A hybrid analog/digital phase-lock loop with high-level event synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level and synchronizing the output clock to high-level events. A numerically-controlled analog oscillato |
| 7596681 |
Processor and processing method for reusing arbitrary sections of program code |
September 29, 2009 |
| A processor and processing method for reusing arbitrary sections of program code provides improved upgrade capability for systems with non-alterable read only memory (ROM) and a more flexible instruction set in general. A specific program instruction is provided in the processor inst |
| 7589766 |
Selectable threshold multimode gain control apparatus and method for setting mutually continuous |
September 15, 2009 |
| A selectable threshold multimode gain control apparatus and method for a charge coupled device (CCD) or CMOS imaging system includes an automatic gain control (AGC) circuit which continuously controls gain in said CCD system to produce a mutually continuous combined target gain level. A |
| 7580531 |
Dynamic range reducing volume control |
August 25, 2009 |
| An audio amplifier is provided having a compressor with an automatically-adjustable compressor. Compression is linked to the volume control in an inverse relationship whereby, when the volume is reduced, the compression ratio is increased to boost the listening level of quieter passa |
| 7570118 |
Thermal overload protection circuit and method for protecting switching power amplifier circuits |
August 4, 2009 |
| A thermal overload protection circuit and method for protecting switching power amplifier circuits provides protection against latch-up and other failures due to energy returned from an inductive load when the amplifier output is disabled in response to a thermal overload condition. Upon |
| 7567641 |
Sample rate conversion systems with an independent internal oscillator |
July 28, 2009 |
| Because of the natural ability to reject clock jitter, the SRC circuits include an internal oscillator to provide an operating clock signal. The internal oscillator can be operated independently of any external frequency control signal, including input and output frame clocks. The in |
| 7558358 |
Method and apparatus for generating a clock signal according to an ideal frequency ratio |
July 7, 2009 |
| A method and apparatus for generating a clock signal according to an ideal frequency ratio provides flexible and reduced frequency error clock generation. A ratio control number is specified or is determined from a phase-frequency comparison of the clock signal to a timing reference. A |
| 7557661 |
Direct digital synthesis (DDS) hybrid phase-lock loop for low-jitter synchronization |
July 7, 2009 |
| A direct digital synthesis (DDS) hybrid phase-lock loop for low-jitter synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level. A DDS circuit provides a clock output and has an input for receiving a rational number. |
| 7554473 |
Control system using a nonlinear delta-sigma modulator with nonlinear process modeling |
June 30, 2009 |
| A control system includes a nonlinear delta-sigma modulator, and the nonlinear delta-sigma modulator includes a nonlinear process model that models a nonlinear process in a signal processing system, such as a nonlinear plant. The nonlinear delta-sigma modulator includes a feedback mo |
| 7554409 |
Over-current protection circuit and method for protecting switching power amplifier circuits |
June 30, 2009 |
| An over-current protection circuit protection circuit and method for protecting switching power amplifier circuits provides protection against latch-up and other failures due to energy returned from an inductive load when one or more transistors in the amplifier output are disabled in |
| 7554399 |
Protection circuit and method for protecting switching power amplifier circuits during reset |
June 30, 2009 |
| A protection circuit and method for protecting switching power amplifier circuits during reset provides protection against latch-up and other failures due to energy returned from an inductive load when the amplifier is reset. Upon receipt of a reset indication, rather than immediately |
| 7545946 |
Method and system for surround sound beam-forming using the overlapping portion of driver freque |
June 9, 2009 |
| A method and system for surround sound beam-forming using the overlapping portion of driver frequency ranges provides a low cost alternative to present external surround array systems. The overlapping frequency range of a pair of speaker drivers, generally a low-frequency and a high- |
| 7538823 |
Luminance/chrominance video data separation circuits and methods and video systems utilizing the |
May 26, 2009 |
| A method of separating a chroma data component from a video data stream includes determining a phase relationship between a color burst in digital video data samples of a composite video signal and a local clock signal which processes the digital video data samples. In response to de |
| 7535396 |
Digital-to-analog converter (DAC) having filter sections with differing polarity |
May 19, 2009 |
| A digital-to-analog converter (DAC) having filter sections with differing polarity provides a low-noise, low area bipolar output solution in delta-sigma modulator based DACs. A shift register receives an input bit-stream and provides a series of tap outputs that are used to control a |
| 7522193 |
Histogram-based automatic gain control method and system for video applications |
April 21, 2009 |
| An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit |
| 7521951 |
Non-invasive, low pin count test circuits and methods utilizing emulated stress conditions |
April 21, 2009 |
| A method of testing an internal block of an integrated circuit includes initiating a test mode and verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the |
| 7515076 |
Method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit i |
April 7, 2009 |
| A method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog to digital converter (ADC) provides for reduced noise in the ADC conversions. Sampling circuits of the ADC are operated by sampling clock signals and digital circuits and |
| 7499106 |
Method and system for synchronizing video information derived from an asynchronously sampled vid |
March 3, 2009 |
| A method and system for synchronizing video information derived from an asynchronously sampled video signals provide a mechanism for using asynchronous sampling in the front-end of digital video capture systems. A ratio between the sampling clock frequency and the source video clock |
| 7492296 |
Discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with input signa |
February 17, 2009 |
| A discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with input signal and common-mode current nulling, provides a high input impedance level substantially independent of input capacitor size and input signal gain setting. An input voltage is sampled using on |
| 7489263 |
Discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with multi-phase |
February 10, 2009 |
| A discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with multi-phase reference application, provides a high input impedance level substantially independent of input capacitor size and input signal gain setting. An input voltage is sampled at the common mode |
| 7486937 |
Efficient RF amplifier topologies |
February 3, 2009 |
| Power-efficient front-end topologies for radio frequency power amplifiers are described which may be used to implement full-duplex transceivers for wireless mobile terminals such as, for example, cellular phones. At least some of the described topologies employ highly efficient power amp |
| 7477178 |
Power-optimized analog-to-digital converter (ADC) input circuit |
January 13, 2009 |
| A power-optimized analog-to-digital converter (ADC) input circuit provides for optimized power consumption versus performance. The first amplifier stage of the ADC is provided by a plurality of amplifiers that are selectably enabled to provide a particular bandwidth and noise perform |
| 7477088 |
Power supplies for driving h-bridges |
January 13, 2009 |
| An apparatus includes an integrated circuit that includes low side power supply circuitry that provides an output voltage for H-bridge circuitry. The low side power supply circuitry includes one transistor that provides one current to the output of the low side power supply circuitry in |
| 7477079 |
Single ended switched capacitor circuit |
January 13, 2009 |
| A single-ended, non-differential switched capacitor circuit is disclosed which removes the effect of common mode noise. To this end, the circuit creates a capacitance divider using the sampling capacitors, Cs, to create a stable and noise-free common mode voltage (Vcom) signal. Once |
| 7474724 |
Method and system for video-synchronous audio clock generation from an asynchronously sampled vi |
January 6, 2009 |
| A method and system for video-synchronous audio clock generation from an asynchronously sampled video signal provides a mechanism for maintaining synchronization of audio sampling in digital video-audio systems. A ratio between the sampling clock frequency and an audio reference frequenc |
| 7471340 |
Video quality adaptive variable-rate buffering method and system for stabilizing a sampled video |
December 30, 2008 |
| A video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal reduces the buffer size required to compensate for line-to-line variations in an unstable video source. A video signal is sampled at a predetermined rate and decimated by a selec |
| 7466194 |
DC offset mitigation in a single-supply amplifier |
December 16, 2008 |
| An amplifier is described which includes a first loop including a first amplifier stage having an offset voltage associated therewith. An output stage includes two switching devices in a bridge configuration configured to be coupled between a supply voltage and ground. An output of the |
| 7456765 |
Systems and methods for clock mode determination utilizing master clock frequency measurements |
November 25, 2008 |
| A system for determining a data converter clock operating mode includes measurement circuitry which measures a master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the me |
| 7446686 |
Incremental delta-sigma data converters with improved stability over wide input voltage ranges |
November 4, 2008 |
| A method of operating a delta-sigma data converter includes receiving an input signal at an input of a delta-sigma modulator having a loop filter including a plurality of integrator stages, a quantizer for generating a quantized output code from outputs of the integrator stages, and a |
| 7439892 |
Variable voltage generator for delta-sigma modulators |
October 21, 2008 |
| A modulator integrator circuit includes an amplifier having a capacitive feedback connection, a variable voltage generator, a fixed voltage reference, and a capacitor having a first plate and a second plate. The first plate of the capacitor is coupled to the variable voltage generato |
| 7432842 |
Multi-channel pulse width modulated signal interleave and inversion |
October 7, 2008 |
| A multi-channel signal processing system reduces electromagnetic interference (EMI) by staggering pulse edges of one or more pulse-width modulated signals (PWM signals) to prevent pulse edge overlap with at least one of the other PWM signals and inverting at least one of the PWM sign |
| 7429940 |
Delta-sigma modulator circuit with limiter and method therefor |
September 30, 2008 |
| A delta-sigma modulator circuit with limiter and method provide extended dynamic range in noise-shaped pulse generators. A limiting circuit is provided to adjust the output of the quantizer of the delta-sigma modulator according to a given range of values. The range is adjusted in co |
| 7424544 |
Method for improving performance in computer networks based on lossy channel |
September 9, 2008 |
| A method and system for improving networking performance in networks based on lossy channels. A selected file system call 109 is redirected by sending a file request to a server over a first protocol. Data is received from the server in response to the file request over a second prot |
| 7423697 |
Method and apparatus for AC coupling a signal while restoring DC levels |
September 9, 2008 |
| A system in which drooping of the video levels due to leakage currents and proper DC bias level is addressed by providing a charge into the video signal to offset the leakage currents and to provide DC bias. To determine the leakage current level, measurements are made measuring the |
| 7423567 |
Analog-to-digital converter (ADC) having a reduced number of quantizer output levels |
September 9, 2008 |
| An analog-to-digital converter (ADC) having a reduced number of quantizer output levels provides for reduced complexity and power consumption along with improved linearity. The analog-to-digital converter includes a loop filter, a quantizer for quantizing the output of the loop filter an |
| 7411534 |
Analog-to-digital converter (ADC) having integrator dither injection and quantizer output compen |
August 12, 2008 |
| An analog-to-digital converter (ADC) having integrator dither injection and quantizer output compensation reduces the probability of unchanging code sequences that occur when the input signal and feedback signal are equal and thus no quantizer output change occurs. In particular, in |
| 7408490 |
Calibration of a redundant number system successive approximation analog-to-digital converter |
August 5, 2008 |
| A system and method calibrate a redundant number system analog-to-digital converter (RNS ADC) using successive approximations of multiple input signals and approximating each input signal at least twice. The RNS ADC includes N analog converter reference elements, each of the analog c |
| 7405770 |
Adaptive equalization method and system for reducing noise and distortion in a sampled video sig |
July 29, 2008 |
| An adaptive equalization method and system for reducing noise and distortion in a sampled video signal improves the quality of output video information in both consumer and professional applications. A multi-band equalizer applied to the sampled video information reduces noise and di |
| 7400362 |
Method and apparatus to interface video signals to a decoder to compensate for droop |
July 15, 2008 |
| A system in which drooping of the video levels due to leakage currents and proper DC bias level is addressed by providing a charge into the video signal to offset the leakage currents and to provide DC bias. To determine the leakage current level, measurements are made measuring the |
| 7400284 |
Low noise data conversion circuits and methods and systems using the same |
July 15, 2008 |
| A circuit including a first element sampling noise from and discharging noise to a signal line in response to an input signal transitioning on selected edges of a clock signal. A second element samples noise from and discharges noise to the signal line in response to another input signal |
| 7395209 |
Fixed point audio decoding system and method |
July 1, 2008 |
| A digital audio decoder for receiving an encoded audio signal and decoding the audio signal. The digital audio decoder uses both real time computations and calculations pre-stored in a look-up table to decode the encoded audio signal. The digital audio decoder uses fixed point arithm |
| 7391842 |
Direct synthesis clock generation circuits and methods |
June 24, 2008 |
| Clock signal generation circuitry includes input circuitry for receiving a frequency control input signal and a clock signal and generating a memory address therefrom, a memory for storing digital data indexed by the memory address and representing real and imaginary parts of a complex |
| 7391452 |
Successive approximation calibration apparatus, system, and method for dynamic range extender |
June 24, 2008 |
| A gain characteristic correctable dynamic range enhancement system (DRES) receives input signals from an imager device connected to a correlated double sampling (CDS) circuit for receiving the video signal from the CCD imaging device. The dynamic range enhancement system includes a varia |
